Capstone: diagnose hold after CTS
Separate external timing assumptions from real minimum-delay failures before paying for delay cells.
- Lesson
- L8.2
- Time
- 45 min
- Runs on
- OpenROAD
- Check
- 5 questions
The first SDC produces 64 reported minimum violations after clock tree synthesis, while correcting the interface assumptions leaves 27 that still need repair. The reference adds 11 delay cells instead of the 78 added under the original assumptions.
| Decision | CTS violation count | Added hold cells | CTS area |
|---|---|---|---|
| First SDC, no repair | 64 | 0 | 2432.3328 µm² |
| Corrected SDC, no repair | 27 | 0 | 2432.3328 µm² |
| Diagnose, then repair | 0 | 11 | 2542.4384 µm² |
| Repair first | 0 | 78 | 3213.0816 µm² |
Counts come from the tool’s minimum-check summary. The comparison also states its chosen hold margins below.
Read the interface note first
The circuit is the corrected GPIO and timer peripheral from R8.1. Its event bits match the register map, and mapping produces 176 cells and 55 flip-flops; physical design must preserve that behavior.
Starting files: RTL, mapped circuit, and timing constraints. Keep these views together when comparing your work with the reference.
For this exercise, the APB master guarantees data at the block input between 0.15 ns and 2 ns after the reference clock edge. The chosen 12 ns clock and interface requirements include the assumed clock relationship and external path; they are not measurements of a board.
Read the diagram as text
- APB master: Chosen external timing note
- Block data input: 0.15–2 ns after reference edge
- Capture register: Library hold requirement
- Reference clock: 12 ns period
- Propagated clock tree: Measured insertion delay
- APB master → Block data input: External data path
- Block data input → Capture register: Internal minimum data delay
- Reference clock → Propagated clock tree: Clock input
- Propagated clock tree → Capture register: Capture edge arrives later
A positive external minimum delay can help input hold. It must come from the interface guarantee.
The initial SDC assumes zero minimum input delay and 0.5 ns hold uncertainty. The exercise’s uncertainty budget allocates 0.47 ns to an early skew allowance and 0.03 ns to residual uncertainty. Propagated clocks replace that stated skew allowance while the residual requirement remains in every scenario.
Reset release has a separate chosen arrival of 3 ns, and its recovery and removal checks remain enabled. Asynchronous GPIO pins are cut only into their designated first synchronizer stages; the next stages retain ordinary timing. Explain these intended exceptions in the final coverage review.
Repair the remaining physical failures
Hold means new data must not reach the capture register too soon after its active edge. A later capture clock can make an input path fail even with positive data delay. Increasing the clock period usually leaves this same-edge requirement unchanged.
| Change | Reason | What remains |
|---|---|---|
| Input minimum: 0 → 0.15 ns | Match the supplied external guarantee | Internal data delay and capture insertion |
| Hold uncertainty: 0.5 → 0.03 ns | Replace the stated skew allowance with propagated clocks | Residual uncertainty and actual skew |
| Enable hold repair | Delay the remaining short paths | Setup, area and corner checks |
The numerical budgets are chosen for this exercise. They are not a universal post-CTS recipe.
With those corrections, detailed-route TT minimum slack is -0.0579 ns before repair. The reference enables repair with a chosen 0.1 ns hold margin. Its CTS repair adds 11 cells and 110.1056 µm².
The comparison that repairs first uses a 0.03 ns margin. Applying the larger margin to its exaggerated requirements reaches the tool’s buffer-count limit. This is not a perfectly controlled margin experiment; both settings and the failed attempt belong in the engineering record.
Delay cells consume area and can lengthen setup paths, while their delay also changes with the cell corner. A repair measured at typical conditions therefore needs a fresh fast and slow analysis; selecting only the corner that passes would conceal the trade.
The repair-first attempt still has -0.8800 ns maximum slack at the cold slow corner, and its fast-corner minimum slack is -0.3189 ns. Spending more area did not make its original requirements pass every corner.
Three hints
Hint 1
Identify whether the failing path starts at an input port or a register.
Hint 2
Reconstruct the external timing guarantee before changing a delay number.
Hint 3
Repair after correcting the assumptions, then inspect setup and all minimum checks across corners.
Compare the final reports
- Tap cells
- Logic
- Buffers and inverters
- Flip-flops
- Clock tree
- Clock nets
- met1
- met2
- met3
- met4
- I/O pins
- Stage
- Floorplan
- Cell area
- 2,326.0 µm²
- Utilization
- 42.5 %
- Worst max slack
- 6.6026 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.0168 ns
- Stage
- Global placement
- Cell area
- 2,326.0 µm²
- Utilization
- 42.5 %
- Wirelength (HPWL)
- 3,088 µm
- Worst max slack
- 5.9553 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.0254 ns
- Overflow
- 0.0983
- Stage
- Detailed placement
- Cell area
- 2,326.0 µm²
- Utilization
- 42.5 %
- Wirelength (HPWL)
- 3,696 µm
- Worst max slack
- 6.0258 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.0236 ns
- Stage
- Clock tree
- Cell area
- 2,542.4 µm²
- Utilization
- 46.5 %
- Wirelength (HPWL)
- 4,013 µm
- Worst max slack
- 6.0193 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.1412 ns
- Clock skew
- 0.1040 ns
- Stage
- Global route
- Cell area
- 2,542.4 µm²
- Utilization
- 46.5 %
- Wirelength (HPWL)
- 4,013 µm
- Routed wirelength
- 8,300 µm
- Worst max slack
- 5.8414 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.1591 ns
- Routing usage
- 14.6 %
- Overflow
- 0
- Stage
- Detailed route
- Cell area
- 2,542.4 µm²
- Utilization
- 46.5 %
- Wirelength (HPWL)
- 4,013 µm
- Routed wirelength
- 5,013 µm
- Worst max slack
- 5.9793 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.1550 ns
- Routing violations
- 0
- Detailed placement
Before the clock tree, the data paths and original mapped cells are placed.
- Clock tree
The actual capture clock creates the minimum-delay requirements. Repair adds measured delay cells.
- Detailed route
The completed route is extracted and rechecked. Read the reports beside this geometry.
Read the layout as text
gpio_timer: die 84.77 × 84.77 µm, core 74.52 × 73.44 µm, 27 rows of 2.72 µm, 135 signal pins.
| Stage | Cell area | Utilization | Wirelength (HPWL) | Routed wirelength | Worst max slack | Total negative max slack | Worst min slack | Clock skew | Routing usage | Overflow | Routing violations | Cells placed |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Floorplan | 2,326.0 µm² | 42.5 % | — | — | 6.6026 ns | 0.0000 ns | 0.0168 ns | — | — | — | — | 72 tap cells; I/O pins not placed yet |
| Global placement | 2,326.0 µm² | 42.5 % | 3,088 µm | — | 5.9553 ns | 0.0000 ns | 0.0254 ns | — | — | 0.0983 | — | 72 tap cells, 1 buffers and inverters, 120 logic, 55 flip-flops |
| Detailed placement | 2,326.0 µm² | 42.5 % | 3,696 µm | — | 6.0258 ns | 0.0000 ns | 0.0236 ns | — | — | — | — | 72 tap cells, 1 buffers and inverters, 120 logic, 55 flip-flops |
| Clock tree | 2,542.4 µm² | 46.5 % | 4,013 µm | — | 6.0193 ns | 0.0000 ns | 0.1412 ns | 0.1040 ns | — | — | — | 72 tap cells, 12 buffers and inverters, 120 logic, 55 flip-flops, 7 clock tree |
| Global route | 2,542.4 µm² | 46.5 % | 4,013 µm | 8,300 µm | 5.8414 ns | 0.0000 ns | 0.1591 ns | — | 14.6 % | 0 | — | 72 tap cells, 12 buffers and inverters, 120 logic, 55 flip-flops, 7 clock tree |
| Detailed route | 2,542.4 µm² | 46.5 % | 4,013 µm | 5,013 µm | 5.9793 ns | 0.0000 ns | 0.1550 ns | — | — | — | 0 | 72 tap cells, 12 buffers and inverters, 120 logic, 55 flip-flops, 7 clock tree |
The buffer-colored cells include clock and data buffers. The report counts identify the hold-repair additions.
| Cell corner / same extracted wires | Worst max slack | Worst min slack | Slew / cap / fanout |
|---|---|---|---|
| tt_025C_1v80 | 5.9793 ns | 0.155 ns | 0 / 0 / 0 |
| ss_100C_1v60 | 4.1192 ns | 0.2434 ns | 10 / 1 / 0 |
| ss_n40C_1v60 | 3.1051 ns | 0.1652 ns | 20 / 2 / 0 |
| ff_n40C_1v95 | 6.6814 ns | 0.0995 ns | 0 / 0 / 0 |
Timing clears at the available cell corners; remaining slow-corner electrical violations still require work.
Reference walk-through
Save the first report, correct the minimum input delay from the interface note, and replace only the stated skew allowance before rerunning with repair disabled. That separates the effect of each assumption from the cost of inserted cells.
Enable hold repair, route and extract, then inspect every available corner. Record the final area and remaining electrical failures alongside the intended GPIO synchronizer exceptions, reset checks and supply endpoints before using the L7.6 handoff checklist.
The live exercise stops after CTS with repair disabled. Change the two suspect assumptions separately, then compare the remaining failure with the repaired reference above. The routed figures include additional wire extraction, so their final slack need not equal the live placement estimate.
Asked in interviews
What comes before a large hold repair?
Check clock propagation, external minimum delays, uncertainty components and exception coverage. Then repair the justified failures.
May an input delay be increased until timing passes?
Only if the external interface guarantees that value. Otherwise the change hides a real physical requirement.
Why can the slow corner matter for minimum timing?
Capture-clock delay, data delay and library checks all change. The most negative minimum slack need not occur at the fastest cell view.
Try it
The initial CTS minimum slack is -0.6831 ns. Correct the external timing and residual uncertainty before deciding on repair.
A clock-tree result uses estimated wires. The extracted corner table is a separate reference.
Run to draw the timing paths here.
Run the flow to see each stage of the layout here.
clock tree worst minimum slack -0.6831 nsRead the netlist: gpio_timer.v
module gpio_timer(pclk,presetn,psel,penable,pwrite,paddr,pwdata,pstrb,pprot,pready,prdata,pslverr,gpio_in,gpio_out,gpio_oe,irq);
input pclk;
input presetn;
input psel;
input penable;
input pwrite;
input [31:0] paddr;
input [31:0] pwdata;
input [3:0] pstrb;
input [2:0] pprot;
input [7:0] gpio_in;
output pready;
output [31:0] prdata;
output pslverr;
output [7:0] gpio_out;
output [7:0] gpio_oe;
output irq;
wire n0,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n105,n106,n107,n108,n109,n110,n111,n112,n113,n114,n115,n116,n117,n118,n119,n120,n121,n122,n123,n124,n125,n126,n127,n128,n129,n130,n131,n132,n133,n134,n135,n136,n137,n138,n139,n140,n141,n142,n143,n144,n145,n146,n147;
assign prdata[9]=prdata[8];
assign prdata[10]=prdata[8];
assign prdata[11]=prdata[8];
assign prdata[12]=prdata[8];
assign prdata[13]=prdata[8];
assign prdata[14]=prdata[8];
assign prdata[15]=prdata[8];
assign prdata[16]=prdata[8];
assign prdata[17]=prdata[8];
assign prdata[18]=prdata[8];
assign prdata[19]=prdata[8];
assign prdata[20]=prdata[8];
assign prdata[21]=prdata[8];
assign prdata[22]=prdata[8];
assign prdata[23]=prdata[8];
assign prdata[24]=prdata[8];
assign prdata[25]=prdata[8];
assign prdata[26]=prdata[8];
assign prdata[27]=prdata[8];
assign prdata[28]=prdata[8];
assign prdata[29]=prdata[8];
assign prdata[30]=prdata[8];
assign prdata[31]=prdata[8];
sky130_fd_sc_hd__clkinv_1 c0(.A(n0),.Y(n1));
sky130_fd_sc_hd__nor3_1 c1(.A(paddr[5]),.B(paddr[6]),.C(paddr[7]),.Y(n2));
sky130_fd_sc_hd__nand2_1 c2(.A(paddr[3]),.B(n3),.Y(n4));
sky130_fd_sc_hd__nand2_1 c3(.A(gpio_out[4]),.B(n5),.Y(n6));
sky130_fd_sc_hd__a222oi_1 c4(.A1(n7),.A2(n8),.B1(n9),.B2(gpio_oe[4]),.C1(n10),.C2(n11),.Y(n12));
sky130_fd_sc_hd__nand2_1 c5(.A(n6),.B(n12),.Y(prdata[4]));
sky130_fd_sc_hd__nand2_1 c6(.A(gpio_out[3]),.B(n5),.Y(n13));
sky130_fd_sc_hd__a222oi_1 c7(.A1(n14),.A2(n8),.B1(n9),.B2(gpio_oe[3]),.C1(n10),.C2(n15),.Y(n16));
sky130_fd_sc_hd__nand2_1 c8(.A(n13),.B(n16),.Y(prdata[3]));
sky130_fd_sc_hd__nand2_1 c9(.A(gpio_out[2]),.B(n5),.Y(n17));
sky130_fd_sc_hd__a222oi_1 c10(.A1(n18),.A2(n8),.B1(n9),.B2(gpio_oe[2]),.C1(n10),.C2(n19),.Y(n20));
sky130_fd_sc_hd__nand2_1 c11(.A(n17),.B(n20),.Y(prdata[2]));
sky130_fd_sc_hd__nand2_1 c12(.A(gpio_out[5]),.B(n5),.Y(n21));
sky130_fd_sc_hd__nor2_1 c13(.A(n22),.B(n4),.Y(n23));
sky130_fd_sc_hd__a222oi_1 c14(.A1(n24),.A2(n8),.B1(n9),.B2(gpio_oe[5]),.C1(n10),.C2(n25),.Y(n26));
sky130_fd_sc_hd__nand2_1 c15(.A(n21),.B(n26),.Y(prdata[5]));
sky130_fd_sc_hd__nand2_1 c16(.A(gpio_out[6]),.B(n5),.Y(n27));
sky130_fd_sc_hd__a222oi_1 c17(.A1(n28),.A2(n8),.B1(n9),.B2(gpio_oe[6]),.C1(n10),.C2(n29),.Y(n30));
sky130_fd_sc_hd__nand2_1 c18(.A(n27),.B(n30),.Y(prdata[6]));
sky130_fd_sc_hd__nand2_1 c19(.A(gpio_out[7]),.B(n5),.Y(n31));
sky130_fd_sc_hd__a222oi_1 c20(.A1(n32),.A2(n8),.B1(n9),.B2(gpio_oe[7]),.C1(n10),.C2(n33),.Y(n34));
sky130_fd_sc_hd__nand2_1 c21(.A(n31),.B(n34),.Y(prdata[7]));
sky130_fd_sc_hd__and3_1 c22(.A(psel),.B(penable),.C(n35),.X(pslverr));
sky130_fd_sc_hd__nor3b_1 c23(.A(paddr[3]),.B(n22),.C_N(n3),.Y(n8));
sky130_fd_sc_hd__and3b_1 c24(.A_N(paddr[3]),.B(n36),.C(n3),.X(n9));
sky130_fd_sc_hd__and3_1 c25(.A(paddr[3]),.B(n36),.C(n3),.X(n10));
sky130_fd_sc_hd__nand2_1 c26(.A(pwrite),.B(n10),.Y(n37));
sky130_fd_sc_hd__o31ai_1 c27(.A1(n38),.A2(n39),.A3(n40),.B1(n37),.Y(n35));
sky130_fd_sc_hd__nand4_1 c28(.A(pstrb[0]),.B(pwrite),.C(psel),.D(penable),.Y(n41));
sky130_fd_sc_hd__nor2_1 c29(.A(n35),.B(n41),.Y(n42));
sky130_fd_sc_hd__nand3_1 c30(.A(pwdata[1]),.B(n38),.C(n42),.Y(n43));
sky130_fd_sc_hd__nand2_1 c31(.A(paddr[4]),.B(n2),.Y(n22));
sky130_fd_sc_hd__a22o_1 c32(.A1(n44),.A2(n1),.B1(n43),.B2(n45),.X(n46));
sky130_fd_sc_hd__and3_1 c33(.A(n47),.B(n48),.C(n49),.X(n50));
sky130_fd_sc_hd__and4_1 c34(.A(n51),.B(n47),.C(n48),.D(n49),.X(n52));
sky130_fd_sc_hd__and2_0 c35(.A(n53),.B(n52),.X(n54));
sky130_fd_sc_hd__nand2_1 c36(.A(n55),.B(n54),.Y(n56));
sky130_fd_sc_hd__xor2_1 c37(.A(n57),.B(n56),.X(n58));
sky130_fd_sc_hd__a21oi_1 c38(.A1(n48),.A2(n49),.B1(n47),.Y(n59));
sky130_fd_sc_hd__o21ai_0 c39(.A1(n50),.A2(n59),.B1(n18),.Y(n60));
sky130_fd_sc_hd__xnor2_1 c40(.A(n48),.B(n49),.Y(n61));
sky130_fd_sc_hd__nand2_1 c41(.A(n62),.B(n61),.Y(n63));
sky130_fd_sc_hd__nor2_1 c42(.A(paddr[0]),.B(paddr[1]),.Y(n64));
sky130_fd_sc_hd__o211ai_1 c43(.A1(n62),.A2(n48),.B1(n49),.C1(n65),.Y(n66));
sky130_fd_sc_hd__a31oi_1 c44(.A1(n47),.A2(n48),.A3(n49),.B1(n51),.Y(n67));
sky130_fd_sc_hd__or2_0 c45(.A(n52),.B(n67),.X(n68));
sky130_fd_sc_hd__nor3_1 c46(.A(n14),.B(n52),.C(n67),.Y(n69));
sky130_fd_sc_hd__nor3_1 c47(.A(n18),.B(n50),.C(n59),.Y(n70));
sky130_fd_sc_hd__a311oi_1 c48(.A1(n60),.A2(n63),.A3(n66),.B1(n69),.C1(n70),.Y(n71));
sky130_fd_sc_hd__xnor2_1 c49(.A(n53),.B(n52),.Y(n72));
sky130_fd_sc_hd__a22o_1 c50(.A1(n14),.A2(n68),.B1(n72),.B2(n7),.X(n73));
sky130_fd_sc_hd__xnor2_1 c51(.A(n55),.B(n54),.Y(n74));
sky130_fd_sc_hd__or2_0 c52(.A(n7),.B(n72),.X(n75));
sky130_fd_sc_hd__nand2_1 c53(.A(paddr[2]),.B(n64),.Y(n76));
sky130_fd_sc_hd__o221ai_1 c54(.A1(n71),.A2(n73),.B1(n74),.B2(n24),.C1(n75),.Y(n77));
sky130_fd_sc_hd__nand2_1 c55(.A(n24),.B(n74),.Y(n78));
sky130_fd_sc_hd__a2bb2oi_1 c56(.A1_N(n28),.A2_N(n58),.B1(n77),.B2(n78),.Y(n79));
sky130_fd_sc_hd__a31oi_1 c57(.A1(n57),.A2(n55),.A3(n54),.B1(n80),.Y(n81));
sky130_fd_sc_hd__a22o_1 c58(.A1(n28),.A2(n58),.B1(n81),.B2(n32),.X(n82));
sky130_fd_sc_hd__nor2_1 c59(.A(n32),.B(n81),.Y(n83));
sky130_fd_sc_hd__a41oi_1 c60(.A1(n80),.A2(n57),.A3(n55),.A4(n54),.B1(n83),.Y(n84));
sky130_fd_sc_hd__o21ai_0 c61(.A1(n79),.A2(n82),.B1(n84),.Y(n85));
sky130_fd_sc_hd__nand3_1 c62(.A(pwdata[0]),.B(n38),.C(n42),.Y(n86));
sky130_fd_sc_hd__a22o_1 c63(.A1(n87),.A2(n85),.B1(n86),.B2(n88),.X(n89));
sky130_fd_sc_hd__nor3_1 c64(.A(paddr[3]),.B(n22),.C(n76),.Y(n38));
sky130_fd_sc_hd__nand3_1 c65(.A(paddr[3]),.B(n39),.C(n42),.Y(n90));
sky130_fd_sc_hd__mux2_1 c66(.A0(pwdata[0]),.A1(n87),.S(n90),.X(n91));
sky130_fd_sc_hd__nand2_1 c67(.A(n8),.B(n42),.Y(n92));
sky130_fd_sc_hd__mux2_1 c68(.A0(pwdata[7]),.A1(n32),.S(n92),.X(n93));
sky130_fd_sc_hd__mux2_1 c69(.A0(pwdata[6]),.A1(n28),.S(n92),.X(n94));
sky130_fd_sc_hd__mux2_1 c70(.A0(pwdata[5]),.A1(n24),.S(n92),.X(n95));
sky130_fd_sc_hd__mux2_1 c71(.A0(pwdata[4]),.A1(n7),.S(n92),.X(n96));
sky130_fd_sc_hd__mux2_1 c72(.A0(pwdata[3]),.A1(n14),.S(n92),.X(n97));
sky130_fd_sc_hd__mux2_1 c73(.A0(pwdata[2]),.A1(n18),.S(n92),.X(n98));
sky130_fd_sc_hd__mux2_1 c74(.A0(pwdata[1]),.A1(n62),.S(n92),.X(n99));
sky130_fd_sc_hd__nor4_1 c75(.A(paddr[5]),.B(paddr[4]),.C(paddr[6]),.D(paddr[7]),.Y(n36));
sky130_fd_sc_hd__mux2_1 c76(.A0(pwdata[0]),.A1(n65),.S(n92),.X(n100));
sky130_fd_sc_hd__nor2b_1 c77(.A(paddr[3]),.B_N(n39),.Y(n5));
sky130_fd_sc_hd__nand2_1 c78(.A(n42),.B(n5),.Y(n101));
sky130_fd_sc_hd__mux2_1 c79(.A0(pwdata[7]),.A1(gpio_out[7]),.S(n101),.X(n102));
sky130_fd_sc_hd__mux2_1 c80(.A0(pwdata[6]),.A1(gpio_out[6]),.S(n101),.X(n103));
sky130_fd_sc_hd__mux2_1 c81(.A0(pwdata[5]),.A1(gpio_out[5]),.S(n101),.X(n104));
sky130_fd_sc_hd__mux2_1 c82(.A0(pwdata[4]),.A1(gpio_out[4]),.S(n101),.X(n105));
sky130_fd_sc_hd__mux2_1 c83(.A0(pwdata[3]),.A1(gpio_out[3]),.S(n101),.X(n106));
sky130_fd_sc_hd__mux2_1 c84(.A0(pwdata[2]),.A1(gpio_out[2]),.S(n101),.X(n107));
sky130_fd_sc_hd__mux2_1 c85(.A0(pwdata[1]),.A1(gpio_out[1]),.S(n101),.X(n108));
sky130_fd_sc_hd__and3_1 c86(.A(paddr[2]),.B(n64),.C(n36),.X(n39));
sky130_fd_sc_hd__mux2_1 c87(.A0(pwdata[0]),.A1(gpio_out[0]),.S(n101),.X(n109));
sky130_fd_sc_hd__nand2_1 c88(.A(n9),.B(n42),.Y(n110));
sky130_fd_sc_hd__mux2_1 c89(.A0(pwdata[7]),.A1(gpio_oe[7]),.S(n110),.X(n111));
sky130_fd_sc_hd__mux2_1 c90(.A0(pwdata[6]),.A1(gpio_oe[6]),.S(n110),.X(n112));
sky130_fd_sc_hd__mux2_1 c91(.A0(pwdata[5]),.A1(gpio_oe[5]),.S(n110),.X(n113));
sky130_fd_sc_hd__mux2_1 c92(.A0(pwdata[4]),.A1(gpio_oe[4]),.S(n110),.X(n114));
sky130_fd_sc_hd__mux2_1 c93(.A0(pwdata[3]),.A1(gpio_oe[3]),.S(n110),.X(n115));
sky130_fd_sc_hd__mux2_1 c94(.A0(pwdata[2]),.A1(gpio_oe[2]),.S(n110),.X(n116));
sky130_fd_sc_hd__mux2_1 c95(.A0(pwdata[1]),.A1(gpio_oe[1]),.S(n110),.X(n117));
sky130_fd_sc_hd__mux2_1 c96(.A0(pwdata[0]),.A1(gpio_oe[0]),.S(n110),.X(n118));
sky130_fd_sc_hd__nor3_1 c97(.A(paddr[2]),.B(paddr[0]),.C(paddr[1]),.Y(n3));
sky130_fd_sc_hd__nand2_1 c98(.A(n23),.B(n42),.Y(n119));
sky130_fd_sc_hd__mux2_1 c99(.A0(pwdata[1]),.A1(n120),.S(n119),.X(n121));
sky130_fd_sc_hd__mux2_1 c100(.A0(pwdata[0]),.A1(n122),.S(n119),.X(n123));
sky130_fd_sc_hd__o211ai_1 c101(.A1(n79),.A2(n82),.B1(n84),.C1(n87),.Y(n124));
sky130_fd_sc_hd__nor2_1 c102(.A(n58),.B(n124),.Y(n125));
sky130_fd_sc_hd__nor2_1 c103(.A(n74),.B(n124),.Y(n126));
sky130_fd_sc_hd__nor2_1 c104(.A(n72),.B(n124),.Y(n127));
sky130_fd_sc_hd__nor2_1 c105(.A(n68),.B(n124),.Y(n128));
sky130_fd_sc_hd__nor3_1 c106(.A(n50),.B(n59),.C(n124),.Y(n129));
sky130_fd_sc_hd__nor2_1 c107(.A(n61),.B(n124),.Y(n130));
sky130_fd_sc_hd__and2_0 c108(.A(n2),.B(n3),.X(n40));
sky130_fd_sc_hd__a22o_1 c109(.A1(n45),.A2(n120),.B1(n122),.B2(n88),.X(n131));
sky130_fd_sc_hd__nor2_1 c110(.A(n49),.B(n124),.Y(n132));
sky130_fd_sc_hd__nor2_1 c111(.A(n81),.B(n124),.Y(n133));
sky130_fd_sc_hd__a222oi_1 c112(.A1(n88),.A2(n38),.B1(n8),.B2(n65),.C1(n10),.C2(n44),.Y(n134));
sky130_fd_sc_hd__nand3_1 c113(.A(n87),.B(paddr[3]),.C(n39),.Y(n135));
sky130_fd_sc_hd__a222oi_1 c114(.A1(n122),.A2(n23),.B1(n9),.B2(gpio_oe[0]),.C1(gpio_out[0]),.C2(n5),.Y(n136));
sky130_fd_sc_hd__nand3_1 c115(.A(n134),.B(n135),.C(n136),.Y(prdata[0]));
sky130_fd_sc_hd__a222oi_1 c116(.A1(n62),.A2(n8),.B1(n9),.B2(gpio_oe[1]),.C1(n10),.C2(n137),.Y(n138));
sky130_fd_sc_hd__a222oi_1 c117(.A1(n45),.A2(n38),.B1(n23),.B2(n120),.C1(n5),.C2(gpio_out[1]),.Y(n139));
sky130_fd_sc_hd__nand2_1 c118(.A(n138),.B(n139),.Y(prdata[1]));
sky130_fd_sc_hd__dfrtp_1 c119(.CLK(pclk),.D(n123),.Q(n122),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c120(.CLK(pclk),.D(n121),.Q(n120),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c121(.CLK(pclk),.D(n118),.Q(gpio_oe[0]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c122(.CLK(pclk),.D(n117),.Q(gpio_oe[1]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c123(.CLK(pclk),.D(n116),.Q(gpio_oe[2]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c124(.CLK(pclk),.D(n115),.Q(gpio_oe[3]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c125(.CLK(pclk),.D(n114),.Q(gpio_oe[4]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c126(.CLK(pclk),.D(n113),.Q(gpio_oe[5]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c127(.CLK(pclk),.D(n112),.Q(gpio_oe[6]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c128(.CLK(pclk),.D(n111),.Q(gpio_oe[7]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c129(.CLK(pclk),.D(n131),.Q(irq),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c130(.CLK(pclk),.D(n132),.Q(n49),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c131(.CLK(pclk),.D(n130),.Q(n48),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c132(.CLK(pclk),.D(n129),.Q(n47),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c133(.CLK(pclk),.D(n128),.Q(n51),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c134(.CLK(pclk),.D(n127),.Q(n53),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c135(.CLK(pclk),.D(n126),.Q(n55),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c136(.CLK(pclk),.D(n125),.Q(n57),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c137(.CLK(pclk),.D(n133),.Q(n80),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c138(.CLK(pclk),.D(gpio_in[0]),.Q(n140),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c139(.CLK(pclk),.D(gpio_in[1]),.Q(n141),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c140(.CLK(pclk),.D(gpio_in[2]),.Q(n142),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c141(.CLK(pclk),.D(gpio_in[3]),.Q(n143),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c142(.CLK(pclk),.D(gpio_in[4]),.Q(n144),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c143(.CLK(pclk),.D(gpio_in[5]),.Q(n145),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c144(.CLK(pclk),.D(gpio_in[6]),.Q(n146),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c145(.CLK(pclk),.D(gpio_in[7]),.Q(n147),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c146(.CLK(pclk),.D(n140),.Q(n44),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c147(.CLK(pclk),.D(n141),.Q(n137),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c148(.CLK(pclk),.D(n142),.Q(n19),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c149(.CLK(pclk),.D(n143),.Q(n15),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c150(.CLK(pclk),.D(n144),.Q(n11),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c151(.CLK(pclk),.D(n145),.Q(n25),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c152(.CLK(pclk),.D(n146),.Q(n29),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c153(.CLK(pclk),.D(n147),.Q(n33),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c154(.CLK(pclk),.D(n44),.Q(n0),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c155(.CLK(pclk),.D(n109),.Q(gpio_out[0]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c156(.CLK(pclk),.D(n108),.Q(gpio_out[1]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c157(.CLK(pclk),.D(n107),.Q(gpio_out[2]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c158(.CLK(pclk),.D(n106),.Q(gpio_out[3]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c159(.CLK(pclk),.D(n105),.Q(gpio_out[4]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c160(.CLK(pclk),.D(n104),.Q(gpio_out[5]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c161(.CLK(pclk),.D(n103),.Q(gpio_out[6]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c162(.CLK(pclk),.D(n102),.Q(gpio_out[7]),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c163(.CLK(pclk),.D(n100),.Q(n65),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c164(.CLK(pclk),.D(n99),.Q(n62),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c165(.CLK(pclk),.D(n98),.Q(n18),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c166(.CLK(pclk),.D(n97),.Q(n14),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c167(.CLK(pclk),.D(n96),.Q(n7),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c168(.CLK(pclk),.D(n95),.Q(n24),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c169(.CLK(pclk),.D(n94),.Q(n28),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c170(.CLK(pclk),.D(n93),.Q(n32),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c171(.CLK(pclk),.D(n91),.Q(n87),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c172(.CLK(pclk),.D(n89),.Q(n88),.RESET_B(presetn));
sky130_fd_sc_hd__dfrtp_1 c173(.CLK(pclk),.D(n46),.Q(n45),.RESET_B(presetn));
sky130_fd_sc_hd__conb_1 c174(.HI(pready));
sky130_fd_sc_hd__conb_1 c175(.LO(prdata[8]));
endmodule
Check yourself
Remember
- Correct constraints only from documented interface requirements.
- Replace the stated skew allowance while retaining residual uncertainty.
- Repair the remaining short paths and measure the added cost.
- Positive timing does not waive electrical or coverage checks.