Clock period, setup and hold in one picture

What the clock period has to cover

A flop takes its input at the clock edge. In silicon it needs that input stable for a short time before the edge, the setup time, and a short time after it, the hold time. If D changes inside that window, the flop may store the wrong value or hover between 0 and 1 for a while.

Between two flops sits a path of combinational logic. The value leaves the first flop at one edge and must reach the second before the next edge, minus the setup time. So the period must be at least clock-to-Q plus the path delay plus setup, for every path. The slowest path is the critical path, and it sets the highest clock frequency.

Hold works the other way. It compares the fastest path against the same edge, and the period does not appear in the check. A hold failure stays at any clock speed. The layout flow fixes it by adding delay cells to short paths.

RTL simulation cannot see any of this. Its flops change at the edge with no delay, and its gates have none either. A design that passes at one period passes at every period.

What the levels number counts

Synthesize maps the design to generic gates and then runs ltp -noff. It finds the longest chain of cells from a flop output or input port to a flop input or output port. The answer is a count of cells, which this site calls levels of logic on this flow. For the lab design, Yosys 0.70 prints the path below. The excerpt cuts the middle rows and the routing notes.

Longest topological path in add4 (length=21):
    0: \a [0]
    1: $abc$336$new_n116
    ...
   21: $auto$maccmap.cc:240:synth$8.CO [8]
   ff: \sum [9]

The count has no delays in it, no wires and no technology. A NAND and an XOR count the same. It cannot give a frequency, find a hold problem or see a long wire. What it can do is rank paths: more cells in series usually means more delay, on any technology.

Cut the long path and read the number again

Two levels of adders sit between the inputs and the one register. Put a register between them and each stage has one adder. The longest path then starts at a new flop, s01_q[1], and has 17 levels.

assign s01 = a + b;
assign s23 = c + d;
always_ff @(posedge clk ...)
  sum <= s01 + s23;

always_ff @(posedge clk ...) begin
  s01_q <= a + b;
  s23_q <= c + d;
  sum   <= s01_q + s23_q;
end

Read the trade in the numbers. The path lost 4 levels. The design gained 18 flops and one edge of delay, called latency. The new longest stage is the 9-bit adder, so a third register in front of the first adders would not lower the count. R4.3 shows the method in full.

The lab ships the one-stage tree. Run it: 24 sums checked, 0 wrong. Synthesize: 21 levels. Now register a + b and c + d as s01_q and s23_q, and add those to make sum. Run again: still 0 wrong. Synthesize: 17 levels and 28 flops.

Try it

Each input set is held for three edges and checked at the third. Four sets are printed and 20 random ones are only counted. Every sum is right, including the largest, 1020.

Synthesize reports 125 cells, 10 flops and 21 levels of logic. After the cut it reports 146 cells, 28 flops and 17 levels, and the bench still prints 0 wrong. The function did not change; only the latency and the longest path did.

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic [7:0] a = 0, b = 0, c = 0, d = 0;
  logic [9:0] sum;
  int checked = 0, wrong = 0;
  bit quiet = 0;
  // Apply one set of inputs, hold it for three edges, then compare sum with the model.
  task automatic item(input int w, input int x, input int y, input int z);
    int want;
    a = w; b = x; c = y; d = z;
    want = w + x + y + z;
    repeat (3) tick();
    checked++;
    if (sum != want) wrong++;
    if (!quiet) $display("e%0d %0d+%0d+%0d+%0d = %0d (want %0d)", edge_n, a, b, c, d, sum, want);
  endtask
  add4 dut (.clk(clk), .rst_n(rst_n), .a(a), .b(b), .c(c), .d(d), .sum(sum));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    // the lines are printed by item()
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    item(10, 20, 30, 40);
    item(255, 255, 255, 255);             // the largest sum: 1020 needs 10 bits
    item(200, 100, 50, 25);
    item(1, 2, 3, 4);
    quiet = 1;                            // 20 more, random, counted but not printed
    repeat (20) item($urandom_range(255), $urandom_range(255), $urandom_range(255), $urandom_range(255));
    $display("%0d sums checked, %0d wrong", checked, wrong);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

Check yourself

module add4p (input logic clk, input logic [7:0] a, b, c, d, output logic [9:0] sum);
  logic [8:0] s01_q, s23_q;
  always_ff @(posedge clk) begin
    s01_q <= a + b;               // stage 1: two pair sums
    s23_q <= c + d;
    sum   <= s01_q + s23_q;       // stage 2: the final sum
  end
endmodule
module tb;
  logic clk = 0;
  logic [7:0] a, b, c, d;
  logic [9:0] sum;
  add4p dut (.clk(clk), .a(a), .b(b), .c(c), .d(d), .sum(sum));
  initial begin
    a = 10; b = 20; c = 30; d = 40;
    #1 clk = 1; #1 clk = 0;       // first edge
    a = 1; b = 1; c = 1; d = 1;
    #1 clk = 1; #1 clk = 0;       // second edge
    $display("sum=%0d", sum);
    $finish(0);
  end
endmodule

logic [8:0] s01, s23;
assign s01 = a + b;
assign s23 = c + d;
assign sum = s01 + s23;

assign sum = a + b + c + d;

assign sum = (a + b) + (c + d);

assign sum = 10'(a) + 10'(b) + 10'(c) + 10'(d);

logic [7:0] s01, s23;
assign s01 = a + b;
assign s23 = c + d;
assign sum = s01 + s23;