Stalls, backpressure and the skid buffer

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic       in_valid = 0, out_ready = 1;
  logic [7:0] in_data = 0;
  logic       in_ready, out_valid;
  logic [7:0] out_data;
  int stall_at = 5;                       // the consumer holds out_ready low for this one edge
  int n_in = 0, n_out = 0, last_out = 0, order = 0, e = -1;
  bit seen [1:6];
  // At each edge: what both sides offered just before it, and which beats moved.
  always @(posedge clk) begin
    string note;
    e = e + 1;
    note = "";
    if (rst_n && in_valid && in_ready) begin
      n_in++;
      note = {note, $sformatf("  in %0d", in_data)};
    end
    if (rst_n && out_valid && out_ready) begin
      n_out++;
      note = {note, $sformatf("  out %0d", out_data)};
      if (out_data <= last_out) order++;
      if (out_data >= 1 && out_data <= 6) seen[out_data] = 1;
      last_out = out_data;
    end
    if (e >= 2) $display("e%0d in_valid=%b in_data=%0d in_ready=%b out_valid=%b out_data=%0d out_ready=%b%s",
                         e, in_valid, in_data, in_ready, out_valid, out_data, out_ready, note);
  end
  stage dut (.clk(clk), .rst_n(rst_n), .in_valid(in_valid), .in_data(in_data), .in_ready(in_ready),
             .out_valid(out_valid), .out_data(out_data), .out_ready(out_ready));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    // the lines are printed at each edge by the always block above
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    // The producer offers beats 1 to 6, each until it is taken; the consumer is always
    // ready except at one edge.
    repeat (9) begin
      in_valid  = (n_in < 6);
      in_data   = n_in + 1;
      out_ready = (e + 1 != stall_at);
      tick();
    end
    begin
      string missing;
      missing = "";
      for (int k = 1; k <= 6; k++) if (!seen[k]) missing = {missing, $sformatf(" %0d", k)};
      if (missing == "") missing = " none";
      $display("beats in: %0d, beats out: %0d, missing:%s, out of order: %0d", n_in, n_out, missing, order);
    end
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule