Capstone: a pipelined CRC engine with a levels budget

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic        in_valid = 0, in_first = 0, in_last = 0;
  logic [7:0]  in_data = 0;
  logic [31:0] crc;
  logic        crc_valid;
  logic [31:0] model = 0;                 // the bit-serial model's register
  logic [31:0] want[$];                   // the model's CRC for each finished packet
  int packets = 0, wrong = 0;
  bit watch = 0;                          // 1: print every edge
  int unsigned seed = 11;
  // The model: one bit per step, most significant bit first, polynomial 0x04C11DB7.
  function automatic logic [31:0] model_bit(input logic [31:0] c, input logic b);
    logic top;
    top = c[31] ^ b;
    c = c << 1;
    if (top) c = c ^ 32'h04C11DB7;
    return c;
  endfunction
  // Send one byte (gaps cycles of in_valid = 0 first), and feed it to the model bit by bit.
  task automatic send(input logic [7:0] d, input bit first, input bit last, input int gaps = 0);
    repeat (gaps) begin in_valid = 0; in_first = 0; in_last = 0; in_data = 0; tick(); end
    if (first) model = 32'hFFFFFFFF;
    for (int i = 7; i >= 0; i--) model = model_bit(model, d[i]);
    if (last) want.push_back(model);
    in_valid = 1; in_first = first; in_last = last; in_data = d; tick();
  endtask
  task automatic idle(input int n);
    repeat (n) begin in_valid = 0; in_first = 0; in_last = 0; in_data = 0; tick(); end
  endtask
  crc_engine dut (.clk(clk), .rst_n(rst_n), .in_valid(in_valid), .in_first(in_first), .in_last(in_last),
                  .in_data(in_data), .crc(crc), .crc_valid(crc_valid));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    if (watch) $display("e%0d in_valid=%b first=%b last=%b data=%h crc=%h crc_valid=%b",
                       edge_n, in_valid, in_first, in_last, in_data, crc, crc_valid);
    if (crc_valid) begin
      logic [31:0] w;
      w = want.pop_front();
      packets++;
      if (crc !== w) wrong++;
      if ((watch || packets == 2) && crc === w) $display("e%0d packet %0d crc=%h model=%h ok", edge_n, packets, crc, w);
      if ((watch || packets == 2) && crc !== w) $display("e%0d packet %0d crc=%h model=%h WRONG", edge_n, packets, crc, w);
    end
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    // Packet 1: "123" with a one-cycle gap before the last byte, every edge printed.
    watch = 1;
    send("1", 1, 0); send("2", 0, 0); send("3", 0, 1, 1);
    idle(2);
    watch = 0;
    // Packet 2: "123456789" back to back.
    send("1", 1, 0);
    for (int k = 2; k <= 8; k++) send(8'h30 + k, 0, 0);
    send("9", 0, 1);
    idle(2);
    // 30 more packets of 1 to 16 random bytes, with random gaps, checked but not printed.
    for (int p = 0; p < 30; p++) begin
      int len;
      seed = seed * 1103515245 + 12345; len = 1 + seed[19:16];
      for (int k = 0; k < len; k++) begin
        seed = seed * 1103515245 + 12345;
        send(seed[23:16], k == 0, k == len - 1, seed[25:24] == 0 ? 1 : 0);
      end
    end
    idle(3);
    $display("%0d packets, %0d wrong", packets, wrong);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule