Memory inference and read ports

What an array becomes

An unpacked array such as logic [7:0] mem [16], written in a clocked block, is a memory: words selected by an address. The synthesizer first collects it as one memory cell with a write port and a read port. What happens next depends on the flow.

The pinned flow runs memory -nomap to collect the array, then memory_map, which builds word-wide flops and address decoders. It has no memory library to map to. A real ASIC flow gives the synthesizer a library of SRAM macros: dense memory blocks made by a memory compiler and placed like one big cell. Yosys can map to such cells with memory_libmap, but only when a library describes them.

Three read ports, one write

The read port is the design choice. A combinational (asynchronous) read returns mem[raddr] in the same cycle. A synchronous read puts a register in the path and returns the word one cycle later. The register can hold the address or the data.

assign rdata = mem[raddr];

logic [3:0] raddr_q;
always_ff @(posedge clk) raddr_q <= raddr;
assign rdata = mem[raddr_q];

A read-during-write happens when one cycle writes and reads the same address. The memory may return the old word or the new one, and the brief must say which. The lab writes 0xa5 into word 5 while reading word 5, which held 0x55.

The lab: a register file

Run the lab. The bench writes 0x00, 0x11, up to 0xff, reads words 3, 9 and 12, then reads word 5 while writing it. Then change the read to the registered address of the compare and run again: every word arrives one edge later, and the read-during-write returns the new word.

Synthesize each, then change DEPTH to 4 and to 64 and synthesize again. The flops follow the bits exactly. The read mux follows the depth: each output bit chooses among DEPTH flops.

Try it

Edges 0 to 15 write the pattern. Each later line shows the read address of the cycle that ended at that edge, and rq, the word a register captured there. A combinational read needs no extra cycle, so each address meets its own word.

With the registered address, the lines read 0x00, 0x33, 0x99, 0xcc, then 0xa5 at edges 20 and 21. With the registered data, they read 0x00, 0x33, 0x99, 0xcc, 0x55 and 0xa5.

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic       we = 0;
  logic [3:0] waddr = 0, raddr = 0;
  logic [7:0] wdata = 0, rdata;
  logic [7:0] rq;                // a register after the read port: what it captures at each edge
  always @(posedge clk) rq <= rdata;
  bit show = 0;
  task automatic write(input logic [3:0] a, input logic [7:0] d);
    we = 1; waddr = a; wdata = d; tick(); we = 0;
  endtask
  regfile dut (.clk(clk), .we(we), .waddr(waddr), .wdata(wdata), .raddr(raddr), .rdata(rdata));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    if (show && we) $display("e%0d raddr=%0d write %0d<-0x%h rq=0x%h", edge_n, raddr, waddr, wdata, rq);
    else if (show)  $display("e%0d raddr=%0d rq=0x%h", edge_n, raddr, rq);
  endtask
  initial begin
    for (int a = 0; a < 16; a++) write(4'(a), 8'(a * 17));   // 0x00, 0x11, ... 0xff
    show = 1;
    raddr = 3;  tick();
    raddr = 9;  tick();
    raddr = 12; tick();
    we = 1; waddr = 5; wdata = 8'ha5; raddr = 5; tick();       // read and write address 5 in one cycle
    we = 0; tick();
    tick();
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

Check yourself

// regfile: DEPTH words of WIDTH bits, one write port and one read port.
// The write lands at the rising edge when we is 1. The read is combinational:
// rdata follows raddr in the same cycle, with no clock in the path.
module regfile #(parameter int DEPTH = 16, parameter int WIDTH = 8) (
  input  logic                     clk,
  input  logic                     we,
  input  logic [$clog2(DEPTH)-1:0] waddr,
  input  logic [WIDTH-1:0]         wdata,
  input  logic [$clog2(DEPTH)-1:0] raddr,
  output logic [WIDTH-1:0]         rdata
);
  logic [WIDTH-1:0] mem [DEPTH];          // the storage: no reset, like a real RAM

  always_ff @(posedge clk)
    if (we) mem[waddr] <= wdata;          // the write port

  assign rdata = mem[raddr];              // the read port: combinational
endmodule

module tb;
  logic clk = 0, we = 0;
  logic [3:0] waddr = 0, raddr = 0;
  logic [7:0] wdata = 0, rdata, rq;
  regfile dut (.*);
  always @(posedge clk) rq <= rdata;            // a register after the read port
  initial begin
    we = 1; waddr = 2; wdata = 8'h3c;           // write 0x3c into word 2
    #1 clk = 1; #1 clk = 0;
    wdata = 8'hc3; raddr = 2;                   // next cycle: write 0xc3 into word 2 and read word 2
    #1 clk = 1; #1 clk = 0;
    $display("rq=0x%h", rq);
    $finish(0);
  end
endmodule

  always_ff @(posedge clk) rdata <= mem[raddr];

  logic [3:0] raddr_q;
  always_ff @(posedge clk) raddr_q <= raddr;
  assign rdata = mem[raddr_q];

  logic [7:0] word;
  assign word = mem[raddr];
  always_ff @(posedge clk) rdata <= word;

  logic [3:0] raddr_q;
  always_ff @(posedge clk) begin
    raddr_q <= raddr;
    rdata   <= mem[raddr_q];
  end