FIFO depth from burst arithmetic

// sync_fifo: the FIFO of R5.2 with a count register, so DEPTH may be any value from 2 up,
// and a sticky overflow flag: 1 from the first edge where a write is offered while full.
module sync_fifo #(parameter int DEPTH = 4, parameter int WIDTH = 8) (
  input  logic             clk,
  input  logic             rst_n,         // asynchronous, active-low
  input  logic             write_en,
  input  logic [WIDTH-1:0] write_data,
  input  logic             read_en,
  output logic [WIDTH-1:0] read_data,
  output logic             read_valid,
  output logic             full,
  output logic             empty,
  output logic             overflow       // a write was refused: a word was lost
);
  localparam int AW = $clog2(DEPTH);      // address bits
  localparam int CW = $clog2(DEPTH + 1);  // count bits: 0 to DEPTH

  logic [WIDTH-1:0] mem [DEPTH];
  logic [AW-1:0]    wptr_q, rptr_q;
  logic [CW-1:0]    used_q;               // words held

  assign empty = (used_q == '0);
  assign full  = (used_q == CW'(DEPTH));

  wire take_w = write_en && !full;
  wire take_r = read_en && !empty;

  // A pointer wraps from DEPTH - 1 to 0, so DEPTH need not be a power of two.
  function automatic logic [AW-1:0] next(input logic [AW-1:0] p);
    return (p == AW'(DEPTH - 1)) ? '0 : p + 1'b1;
  endfunction

  always_ff @(posedge clk)
    if (take_w) mem[wptr_q] <= write_data;

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin
      wptr_q <= '0; rptr_q <= '0; used_q <= '0;
      read_valid <= 1'b0; read_data <= '0; overflow <= 1'b0;
    end else begin
      if (take_w) wptr_q <= next(wptr_q);
      if (take_r) begin
        rptr_q    <= next(rptr_q);
        read_data <= mem[rptr_q];
      end
      read_valid <= take_r;
      if (take_w && !take_r)      used_q <= used_q + 1'b1;
      else if (take_r && !take_w) used_q <= used_q - 1'b1;
      if (write_en && full) overflow <= 1'b1;
    end
endmodule
`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic       write_en = 0, read_en = 0;
  logic [7:0] write_data = 0, read_data;
  logic       read_valid, full, empty, overflow;
  // One traffic pattern: a burst of b words, one per cycle from cycle 0; the consumer waits s
  // cycles, then reads in the last cycle of every c. The bench counts what the FIFO holds.
  int held, most, lost;
  task automatic pattern(input int b, input int c, input int s);
    int t;
    bit wf, re_ok;
    rst_n = 0; #1 rst_n = 1;                 // empty the FIFO and clear overflow
    held = 0; most = 0; lost = 0; t = 0;
    while (t < b || held > 0) begin
      write_en = (t < b); write_data = 8'(t);
      read_en  = (t >= s) && ((t - s) % c == c - 1);
      wf = full; re_ok = read_en && !empty;   // the flags before the edge
      tick();
      if (write_en && wf) lost++;
      held = held + (write_en && !wf) - re_ok;
      if (held > most) most = held;
      t++;
    end
    write_en = 0; read_en = 0;
  endtask
  sync_fifo dut (.clk(clk), .rst_n(rst_n), .write_en(write_en), .write_data(write_data), .read_en(read_en),
                .read_data(read_data), .read_valid(read_valid), .full(full), .empty(empty), .overflow(overflow));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    pattern(8, 2, 0);
    $display("lost %0d", lost);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule