Capstone: a two-input packet merger

// merger: joins two packet streams, A and B, into one. A word moves on a port at an edge where
// its valid and ready are both 1; the word that carries last = 1 ends its packet.

// fifo: DEPTH words of W bits, first in, first out. This lesson's own small FIFO: dout shows
// the oldest word in the same cycle (first-word fall-through), so the arbiter can see it.
module fifo #(parameter int W = 9, parameter int DEPTH = 4) (
  input  logic         clk,
  input  logic         rst_n,
  input  logic         push,         // write din at this edge (ignored when full)
  input  logic [W-1:0] din,
  output logic         full,
  input  logic         pop,          // drop the oldest word at this edge (ignored when empty)
  output logic [W-1:0] dout,         // the oldest word
  output logic         empty
);
  localparam int AW = $clog2(DEPTH);
  logic [W-1:0] mem [DEPTH];
  logic [AW:0]  wr_q, rd_q;          // one extra bit tells full from empty
  assign empty = (wr_q == rd_q);
  assign full  = (wr_q[AW] != rd_q[AW]) && (wr_q[AW-1:0] == rd_q[AW-1:0]);
  assign dout  = mem[rd_q[AW-1:0]];
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin
      wr_q <= '0; rd_q <= '0;
    end else begin
      if (push && !full)  wr_q <= wr_q + 1'b1;
      if (pop  && !empty) rd_q <= rd_q + 1'b1;
    end
  always_ff @(posedge clk)                 // the storage has no reset
    if (push && !full) mem[wr_q[AW-1:0]] <= din;
endmodule

module merger (
  input  logic       clk,
  input  logic       rst_n,              // active-low, asynchronous
  input  logic       a_valid,
  input  logic [7:0] a_data,
  input  logic       a_last,
  output logic       a_ready,
  input  logic       b_valid,
  input  logic [7:0] b_data,
  input  logic       b_last,
  output logic       b_ready,
  output logic       o_valid,
  output logic [7:0] o_data,
  output logic       o_last,
  input  logic       o_ready
);
  logic [8:0] a_word, b_word, word;      // {last, data}
  logic       a_empty, b_empty, a_full, b_full;
  logic       pick_b;                    // 1: the next word comes from B
  logic       take;                      // a word moves into the output register at this edge

  fifo #(.W(9), .DEPTH(4)) u_fa (.clk(clk), .rst_n(rst_n), .push(a_valid), .din({a_last, a_data}), .full(a_full),
                                 .pop(take && !pick_b), .dout(a_word), .empty(a_empty));
  fifo #(.W(9), .DEPTH(4)) u_fb (.clk(clk), .rst_n(rst_n), .push(b_valid), .din({b_last, b_data}), .full(b_full),
                                 .pop(take && pick_b), .dout(b_word), .empty(b_empty));
  assign a_ready = !a_full;
  assign b_ready = !b_full;

  // The arbiter: round robin between the two FIFOs, one packet at a time.
  logic last_b_q;                        // the last word taken came from B
  logic open_q;                          // a packet has started and its last word has not left
  always_comb begin
    if (open_q)                    pick_b = last_b_q;   // finish the open packet first
    else if (!a_empty && !b_empty) pick_b = !last_b_q;  // both have a word: the other port's turn
    else                           pick_b = !b_empty;   // only one has a word (or none)
  end
  assign word = pick_b ? b_word : a_word;           // the 2:1 mux
  assign take = (pick_b ? !b_empty : !a_empty) && (!o_valid || o_ready);

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin
      last_b_q <= 1'b1; open_q <= 1'b0;  // so that A goes first after reset
    end else if (take) begin
      last_b_q <= pick_b;
      open_q   <= !word[8];              // open until the word with last leaves
    end

  // The output register: it loads when it is empty or its word is leaving.
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin
      o_valid <= 1'b0; o_data <= '0; o_last <= 1'b0;
    end else if (take) begin
      o_valid <= 1'b1; {o_last, o_data} <= word;
    end else if (o_ready) begin
      o_valid <= 1'b0;
    end
endmodule

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic       a_valid = 0, a_last = 0, b_valid = 0, b_last = 0, o_ready = 0;
  logic [7:0] a_data = 0, b_data = 0;
  logic       a_ready, b_ready, o_valid, o_last;
  logic [7:0] o_data;
  bit         quiet = 1;
  int len_a[$] = '{2, 2}, len_b[$] = '{2, 2};   // packet lengths in words
  int pa = 0, wa = 0, pb = 0, wb = 0;     // the packet and word each source offers next
  int next_a = 0, next_b = 0;             // the {packet, word} each port should deliver next
  int first_port = -1, mixed = 0, packets = 0, cut = 0, order = 0, from_a = 0, from_b = 0;
  string line = "", order_s = "order:";
  function automatic string name(input logic [7:0] w);
    return $sformatf("%s%0d.%0d", w[7] ? "B" : "A", w[6:4], w[3:0]);
  endfunction
  merger dut (.clk(clk), .rst_n(rst_n), .a_valid(a_valid), .a_data(a_data), .a_last(a_last), .a_ready(a_ready),
              .b_valid(b_valid), .b_data(b_data), .b_last(b_last), .b_ready(b_ready),
              .o_valid(o_valid), .o_data(o_data), .o_last(o_last), .o_ready(o_ready));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    if (edge_n >= 2) begin
      // The sources offer their next words and hold them until ready; the consumer may stall.
      a_valid = (pa < len_a.size()) && !(0);
      a_data  = {1'b0, 3'(pa), 4'(wa)};  a_last = a_valid && (wa == len_a[pa] - 1);
      b_valid = (pb < len_b.size());
      b_data  = {1'b1, 3'(pb), 4'(wb)};  b_last = b_valid && (wb == len_b[pb] - 1);
      o_ready = !(0);
      #1;
      if (a_valid && a_ready) begin wa++; if (a_last) begin pa++; wa = 0; end end
      if (b_valid && b_ready) begin wb++; if (b_last) begin pb++; wb = 0; end end
      if (o_valid && o_ready) begin                // this word leaves at the next edge
        if (first_port < 0) first_port = o_data[7];
        else if (o_data[7] != first_port) mixed = 1;
        if (o_data[7]) begin if (o_data[6:0] != next_b) order++; next_b = o_last ? (o_data[6:4] + 1) * 16 : o_data[6:0] + 1; end
        else           begin if (o_data[6:0] != next_a) order++; next_a = o_last ? (o_data[6:4] + 1) * 16 : o_data[6:0] + 1; end
        line = {line, line == "" ? "" : " ", name(o_data)};
        if (o_last) begin
          packets++; if (mixed) cut++;
          if (o_data[7]) from_b++; else from_a++;
          order_s = {order_s, $sformatf(" %s%0d", o_data[7] ? "B" : "A", o_data[6:4])};
          if (!quiet && mixed) $display("e%0d %s  cut", edge_n + 1, line);
          else if (!quiet)     $display("e%0d %s", edge_n + 1, line);
          line = ""; first_port = -1; mixed = 0;
        end
      end
    end
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    repeat (20) tick();
    $display("%s", order_s);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule