ASIC Point

Silicon Lab

Design Verification Problems

Build a design, hunt its bugs, or repair what fails. Every answer runs on a real simulator.

Build starts from a specification: make it work, then make it small or fast. Bug Hunt asks for the checker or the test that catches broken designs. Repair hands you a failure: find the cause, then fix the design.

Module 1 · Storing Data

  1. 1.5.6 Catch the broken formatters 825 Break It Easy Browser
  2. 1.6.6 Addresses that catch broken decoders 1050 Break It Medium Browser

Module 4 · Classes

  1. 4.2.7 Transactions that expose broken compares 1050 Break It Medium Verilator

Module 5 · Randomization

  1. 5.2.6 Operations that expose broken legality checks 1050 Break It Medium Verilator

Module 6 · Connecting to the DUT

  1. 6.5.9 Traces that expose broken hold checkers 900 Break It Easy Verilator

Module 7 · FIFO Verification

  1. 7.1.6 Requests that expose broken FIFO rules 1050 Break It Medium Verilator
  2. 7.6.1 Pointer-wrap sequence 825 Break It Easy Verilator

Protocols · P1 Protocol Fundamentals

  1. P1.11.2 Break the links 1125 Break It Medium Browser

Protocols · P2 AXI

  1. P2.18.2 Break the subordinates 1275 Break It Medium Browser
  2. P2.18.3 Break the managers 1275 Break It Medium Browser