ASIC Point

Silicon Lab

Design Verification Problems

Build a design, hunt its bugs, or repair what fails. Every answer runs on a real simulator.

Build starts from a specification: make it work, then make it small or fast. Bug Hunt asks for the checker or the test that catches broken designs. Repair hands you a failure: find the cause, then fix the design.

Module 2 · Collections

  1. 2.7.8 The stale expectation 1125 Debug Medium Verilator

Module 3 · Routines and Processes

  1. 3.3.6 The timer that outlived its race 1125 Debug Medium Verilator

Module 5 · Randomization

  1. 5.6.6 The burst that changed after the solve 1125 Debug Medium Verilator

Module 6 · Connecting to the DUT

  1. 6.7.1 Identify the sampling race 1125 Debug Medium Verilator

Module 7 · FIFO Verification

  1. 7.4.6 The scoreboard that checks too early 1125 Debug Medium Verilator

Protocols · P1 Protocol Fundamentals

  1. P1.5.1 The throughput that never rose 1200 Debug Medium Browser
  2. P1.6.1 The FIFO that overflowed 1200 Debug Medium Browser
  3. P1.11.3 The beat that arrived late 1200 Debug Medium Browser

Protocols · P2 AXI

  1. P2.4.1 RDATA not held 1200 Debug Medium Browser
  2. P2.12.1 The stale read 1350 Debug Medium Browser
  3. P2.18.4 The beat that landed in the wrong word 1275 Debug Medium Browser