Silicon Lab
Design Verification Problems
Build a design, hunt its bugs, or repair what fails. Every answer runs on a real simulator.
Verify problems
Build starts from a specification: make it work, then make it small or fast. Bug Hunt asks for the checker or the test that catches broken designs. Repair hands you a failure: find the cause, then fix the design.
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Module 1 · Storing Data
- 1.7.6 Catch the bad read paths Verify Medium Browser
Module 3 · Routines and Processes
- 3.7.6 Catch the late responders Verify Hard Verilator
Module 5 · Randomization
- 5.7.9 Catch the generators that cross a bank Verify Medium Verilator
Module 6 · Connecting to the DUT
- 6.2.6 Catch the broken pipelines Verify Medium Verilator
- 6.6.6 Hold the offer Verify Easy Verilator
- 6.6.7 Count the beats Verify Medium Verilator
- 6.6.8 Answer in time Verify Medium Verilator
- 6.6.9 The right data for the right request Verify Medium Verilator
- 6.6.12 Tickets for a lost response Verify Medium Verilator
- 6.6.11 A read-channel assertion suite Verify Hard Verilator
- 6.6.13 A tagged channel assertion suite Verify Hard Verilator
Module 7 · FIFO Verification
- 7.6.6 Catch the FIFOs that break at wrap and reset Verify Hard Verilator
Synchronous FIFO
- H1.9 Catch the faulty FIFOs Verify Hard Browser
Protocols · P1 Protocol Fundamentals
- P1.3.2 Catch the broken sources Verify Hard Browser
- P1.10.1 Properties for the link Verify Hard Verilator
- P1.11.1 Catch every broken link Verify Hard Browser
Protocols · P2 AXI
- P2.2.1 Catch the broken managers Verify Hard Browser
- P2.3.1 The write dependencies Verify Hard Browser
- P2.10.1 The same-ID order checker Verify Hard Browser
- P2.16.1 Six properties for the link Verify Hard Verilator
- P2.18.1 Catch every broken subordinate Verify Hard Browser
UVM Practice
- U5.1.1 Catch the sequencers that grant out of turn Verify Medium UVM
- U7.2.1 A scoreboard among careless listeners Verify Medium UVM
- U16.4.1 The interrupt that clears itself Verify Hard UVM
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