With a current-source load: intrinsic gain

Replace the drain resistor with a PMOS current source, measure the gain one transistor can give, see how length sets it, and learn why such a stage cannot hold its own output level.

Lesson: E3.3
Time: 30 min
Runs on: ngspice
Check: 5 questions

A common-source stage with a PMOS current-source load showed a gain of 63 in AC analysis. The simulator had biased it by a sweep, to a fraction of a millivolt. A 2 mV shift of that input moves the output by 123 mV, and a 1 % change of the load current moves it by 94 mV; no chip holds either that closely.

DC sweepThe output around its bias, 40 mV of inputThe lab stage (NMOS 2/1 µm, PMOS mirror 4/1 µm, 20 µA). The points are the bias and 2 mV either side of it.

Read the plot as a table

Input VIN	v(out)
850 mV	1.506 V
855 mV	1.466 V
860 mV	1.385 V
865 mV	1.172 V
870 mV	861.3 mV
875 mV	586.8 mV
880 mV	411.6 mV
885 mV	321.2 mV
890 mV	275.2 mV

Measured on ngspice 42 (401 of 801 sweep points, 50 µV apart).

The AC gain was right; the output level was never defined by the stage itself.

A current source in place of the resistor

A resistor load buys gain with voltage (E3.2 Common source with a resistor load). A current source gives a different deal: it passes a fixed DC current whatever its voltage, so in the small-signal model it is an open circuit. Only its own output resistance remains, and that can be far larger than any resistor the supply could feed.

The lab builds it from a current mirror. A reference current of 20 µA flows through M3, a PMOS whose gate is tied to its drain (a diode-connected device). M3 sets the gate voltage that carries 20 µA. M2 shares that gate and source, so it carries about the same current into the output. E4 studies mirrors properly; here M2 is simply the load.

Common source with a PMOS current-source loadM3 and M2 form the mirror; M1 amplifies. Node voltages from the lab's operating point.

The reference
IREF pulls 20 µA through M3. Its gate settles where M3 carries exactly that: V_SG = 1.372 V, so the gate line sits at 0.428 V.
20 µA
The copy
M2 has the same gate and source voltages, so it pushes about the same current into the output: 19.76 µA, the small difference coming from its different drain voltage.
19.76 µA
The amplifier
M1 must sink exactly the current M2 pushes. Its gate voltage decides how hard it pulls, and the output moves until the two currents agree.

Read the circuit as text

M3 PMOS transistor (4/1): gate → bp, source → VDD, drain → bp
M2 PMOS transistor (4/1): gate → bp, source → VDD, drain → out
IREF current source (20 µA): + → bp, − → 0
M1 NMOS transistor (2/1): gate → n1, drain → out, source → 0
VIN voltage source: + → n1, − → 0
C_L capacitor (1 pF): pin 1 → out, pin 2 → 0
out port: terminal → out

bp = 0.428 V
out = 0.900 V

NMOS body at ground, PMOS bodies at VDD. W/L in µm.

For the signal, M2's gate is held still by M3, so M2 is just its output resistance r_op. M1 adds its own r_on. The gain is A_v = −g_m·(r_on ‖ r_op): g_m = 132.95 µS, r_on = 695.6 kΩ and r_op = 1.491 MΩ give 63.07, against 63.10 from AC analysis.

Intrinsic gain and length

Suppose the load were ideal, with infinite resistance. The gain would be g_mr_o, set by one transistor alone: its intrinsic gain. Here g_mr_on = 92.5. A real load halves it when r_op = r_on; this PMOS has twice M1's r_o, so the stage keeps 68 % of it.

Write g_mr_o = (g_m/I_D)·(I_Dr_o). The second factor is the Early voltage V_A = I_Dr_o (E2.4 Channel-length modulation and output resistance), and it grows with length. So length sets the gain. The figure runs four stages at 20 µA, each biased by its own sweep.

AC analysisFour lengths, 20 µA each, into 1 pFGain magnitude in dB. NMOS/PMOS W/L in µm: 2/0.15 and 4/0.15, 2/0.5 and 4/0.5, 2/1 and 4/1, 4/2 and 8/2.

L = 0.15 µm
L = 0.5 µm
L = 1 µm
L = 2 µm

Frequency 100 HzL = 0.15 µm = 17.4 dB · L = 0.5 µm = 34.67 dB · L = 1 µm = 36 dB · L = 2 µm = 40.95 dB
Low-frequency gains: 7.42 at L = 0.15 µm, 54.1 at 0.5 µm, 63.1 at 1 µm, 111.5 at 2 µm.
Frequency 21.07 MHzL = 0.15 µm = 6.335 dB · L = 0.5 µm = 2.701 dB · L = 1 µm = -0.02855 dB · L = 2 µm = 0.09529 dB
The curves meet 0 dB between 21 and 45 MHz. The longer stages have far more gain but no more gain-bandwidth.

Read the plot as a table

Frequency	L = 0.15 µm	L = 0.5 µm	L = 1 µm	L = 2 µm
1 Hz	17.4 dB	34.67 dB	36 dB	40.95 dB
10 Hz	17.4 dB	34.67 dB	36 dB	40.95 dB
100 Hz	17.4 dB	34.67 dB	36 dB	40.95 dB
1 kHz	17.4 dB	34.67 dB	36 dB	40.95 dB
10 kHz	17.4 dB	34.67 dB	36 dB	40.93 dB
100 kHz	17.4 dB	34.52 dB	35.62 dB	39.89 dB
1 MHz	17.29 dB	28.1 dB	25.99 dB	26.41 dB
10 MHz	11.77 dB	9.163 dB	6.439 dB	6.565 dB
21.07 MHz	6.335 dB	2.701 dB	-0.02855 dB	0.09529 dB
100 MHz	-6.854 dB	-10.82 dB	-13.55 dB	-13.41 dB
1 GHz	-26.84 dB	-30.8 dB	-33.38 dB	-31.44 dB
10 GHz	-46.67 dB	-48.74 dB	-46.51 dB	-35.72 dB

Measured on ngspice 42 in one run: 181 points, 20 per decade.

L (µm)	Gain	f3	Unity-gain f_u	g_m/I_D	Load V_SG
0.15	7.42	6.14 MHz	45.1 MHz	13.5	0.839 V
0.5	54.1	532 kHz	28.8 MHz	9.35	1.224 V
1	63.1	333 kHz	21.1 MHz	6.73	1.372 V
2 (W doubled)	111.5	191 kHz	21.4 MHz	6.78	1.408 V

Runs of the lab netlist at each size. The unity-gain frequency f_u equals the gain-bandwidth product here.

The gain grows fifteen-fold, but f_u falls from 45 to 21 MHz. That is unfair to the long devices. At a fixed width and current a longer device has a smaller W/L. It needs more overdrive, so its g_m/I_D falls (13.5 to 6.7) and with it g_m and the gain-bandwidth g_m/(2πC_L). Compare at a fixed g_m/I_D instead, widening each device until g_m/I_D ≈ 13.6.

NMOS W/L	PMOS W/L	g_m/I_D	Gain	f_u
2/0.15	4/0.15	13.5	7.42	45.1 MHz
5/0.5	13.33/0.5	13.8	68.3	42.8 MHz
9/1	26.67/1	13.7	133.8	42.8 MHz

The lab netlist with these sizes, 20 µA, 1 pF. W and L in µm.

Now the gain-bandwidth holds near 43-45 MHz while the gain grows eighteen-fold. Length buys gain; g_m/I_D and the load decide speed. The cost is area: the 9/1 device has 30 times the gate area of 2/0.15.

Where the output sits, and how far it swings

Back to the hook. The output is the node where two currents meet: M2 pushes 19.76 µA in, M1 pulls it out. Each sees the node through a large resistance, 474 kΩ together. Any mismatch between the two currents flows through that resistance: a 1 % change of 0.2 µA moves the output by about 0.2 µA × 474 kΩ = 95 mV, and the run measures 94 mV.

The transfer curve shows the same thing from the input side. Its slope at the bias is the gain, so 2 mV at the input moves the output 63 times as much. The higher the gain, the narrower the input window that keeps the output anywhere useful.

DC sweepTransfer curves at L = 0.15 µm and L = 1 µmTwo current-source-loaded stages on one input, 20 µA each. The steeper curve has the higher gain and the narrower input window.

L = 0.15 µm
L = 1 µm

Read the plot as a table

Input VIN	L = 0.15 µm	L = 1 µm
600 mV	1.779 V	1.793 V
650 mV	1.729 V	1.781 V
700 mV	1.437 V	1.759 V
750 mV	1.049 V	1.719 V
800 mV	681.3 mV	1.653 V
850 mV	344.3 mV	1.506 V
900 mV	129.5 mV	229.8 mV
950 mV	81.75 mV	154.7 mV
1 V	62.47 mV	124 mV

Measured on ngspice 42 (801 points, 0.5 mV apart).

So a high-gain stage has no defined output level of its own. The sweep that biased the lab is a simulator luxury. Real circuits use a structure that cancels the mismatch, the differential pair of E5, or feedback that measures the output and corrects the input, E6.

The swing has limits at both ends. Going down, M1 runs out of drain voltage; going up, M2 does. The lab measures where the slope falls to half its peak: the output stays useful from 0.462 V to 1.357 V. At the top the PMOS keeps only 0.44 V across itself. SKY130's PMOS also needs a large gate drive: the mirror sits at V_SG = 1.372 V at L = 1 µm, against 0.839 V at L = 0.15 µm, and the reference must supply it.

Asked in interviews

What is the gain of a common-source stage with a current-source load?
−g_m(r_on ‖ r_op). With equal output resistances it is half the intrinsic gain g_mr_o. Here 63 at L = 1 µm, against an intrinsic gain of 92.5.
What is intrinsic gain, and how do you raise it?
g_mr_o = (g_m/I_D)·V_A, the most one transistor can give. Raise V_A with a longer device, or raise g_m/I_D with a lower current density. A cascode (E3.7) multiplies r_o.
Why is the output DC level of a high-gain stage poorly defined?
Two currents meet at a high-resistance node. Their mismatch times that resistance sets the level, and the input offset times the gain moves it too. A differential pair or feedback must set it.

Try it

Run the netlist and check gain_lf against g_m(r_on ‖ r_op) from the printed values. Open Plots: the DC plot is the whole transfer curve, and its steep part is less than 30 mV wide.

Now change the NMOS to W=9 L=1 and both PMOS devices to W=26.67 L=1, and predict gain_lf and fu before you run. Then set IREF bp 0 20.2u and watch vb move: the sweep finds a new bias, which a real circuit could not.

SPICEngspice 42 · simulator service

Edit the netlist, then run it

Expected measurements: vb = 8.693832e-01 id_b = 1.976049e-05 gm_b = 1.329544e-04 ron_b = 6.955703e+05 rop_b = 1.491436e+06 vsg_b = 1.371995e+00 v_top = 1.357435e+00 v_bottom = 4.621715e-01 gain_lf = 6.309548e+01 f3 = 3.330899e+05 fu = 2.106569e+07

Check yourself

Predict the outputA transistor with g_m = 100 µS and r_o = 1 MΩ drives an ideal current-source load, which is an open circuit for the signal. The run prints the real part of v(out) for 1 V of AC input. Type the line meas prints (format: a = 6.319360e-01).

* g_m = 100 uS into r_o = 1 Mohm: the ideal current-source load adds nothing for the signal
V1 in 0 dc 0 ac 1
G1 out 0 in 0 100u
RO out 0 1meg
.control
ac lin 3 1k 3k
meas ac a FIND vr(out) AT=1k
.endc
.end

ConceptRead the two transfer curves. Which statement do they support?

The L = 1 µm stage falls through its whole output range in a narrower input window than the L = 0.15 µm stageThe L = 1 µm stage reaches a lower output at the end of the sweep, so it swings furtherBoth stages cross 0.9 V at the same input, because they carry the same currentThe L = 0.15 µm stage is steeper, so it has the higher gain

ConceptWhich statement about a common-source stage with a current-source load is wrong?

The gain is close to (g_m/I_D)·V_A when the load resistance is much larger than r_onThe current-source load sets the output DC level, so no bias loop is neededThe load's output resistance r_op appears in parallel with r_on in the gainFor the signal, the load is its output resistance alone

ConceptAt 20 µA and fixed widths, gain rose from 7.4 to 63 when L went from 0.15 to 1 µm, but f_u fell from 45 to 21 MHz. What explains the fall?

The longer PMOS load needs a larger V_SG, which slows how fast the output can moveHigher gain always costs gain-bandwidth in the same proportion, whatever sets the gainA longer L at fixed width lowers W/L, so g_m/I_D and g_m fall, and f_u ≈ g_m/(2πC_L) with themThe output pole moves to a lower frequency as r_o rises, and f_u always tracks that pole

ConceptHow do real circuits give a high-gain stage a defined output level?

By trimming the input bias of every chip at the factory to within a fraction of a millivoltBy sizing the PMOS load very long, so its current is exactBy making the stage's gain lower, so the same mismatch moves the output much lessWith a differential pair that cancels the mismatch, or feedback that sets the input from the output

Remember

A current-source load is an open circuit for the signal; the gain becomes −g_m(r_on ‖ r_op).
Intrinsic gain g_mr_o = (g_m/I_D)·V_A is the most one transistor gives; length raises V_A and so the gain.
Compare lengths at a fixed g_m/I_D: then gain grows with L while the gain-bandwidth g_m/(2πC_L) stays put.
The output of a high-gain stage sits where two currents meet through a large resistance; it needs a differential pair or feedback to be defined.
Swing is limited by M1 at the bottom and by the PMOS load at the top; SKY130's PMOS needs a large V_SG.