ASIC Point

Common gate

Measure the input resistance of a common-gate stage, explain why it depends on the drain load, and use the stage as a current buffer.

Lesson
E3.6
Time
25 min
Runs on
ngspice
Check
5 questions

A current-input stage needed a low input resistance, so the designer chose a common-gate stage: 3.53 kΩ with a 20 kΩ load. To raise its gain, the load became a current source with 20 MΩ of output resistance. The input resistance rose 55 times, to 195 kΩ, and the sensor driving it no longer saw a low-resistance input.

AC analysisInput resistance with two loadsThe same stage (W/L = 4/0.5 µm, 20 µA) with RL = 20 kΩ and with a 20 MΩ current-source load, 1 pF on each drain. A 1 A test current makes the source voltage read in ohms.
  • R_in, 20 kΩ load
  • R_in, 20 MΩ load
1 kΩ10 kΩ100 kΩ1 MΩInput resistance100 Hz1 kHz10 kHz100 kHz1 MHz10 MHz100 MHz1 GHzFrequencyhalf of 195 kΩ1 kΩ10 kΩ100 kΩ1 MΩInput resistance100 Hz10 kHz1 MHz100 MHzFrequencyhalf of 195 kΩ
  1. Frequency 100 HzR_in, 20 kΩ load = 3.53 kΩ · R_in, 20 MΩ load = 194.6 kΩ

    At low frequency the 20 kΩ load gives 3.53 kΩ and the current-source load 195 kΩ. Only the load changed.

  2. Frequency 13.79 kHzR_in, 20 kΩ load = 3.53 kΩ · R_in, 20 MΩ load = 97.22 kΩ

    At 13.8 kHz the current-source case has halved. The 1 pF on the drain starts to short the 20 MΩ.

  3. Frequency 10 MHzR_in, 20 kΩ load = 3.413 kΩ · R_in, 20 MΩ load = 3.342 kΩ

    By 10 MHz the capacitor has shorted both drains, and both inputs read about 3.4 kΩ. The drain no longer moves, so the load no longer matters.

Read the plot as a table
FrequencyR_in, 20 kΩ loadR_in, 20 MΩ load
100 Hz3.53 kΩ194.6 kΩ
1 kHz3.53 kΩ193.1 kΩ
10 kHz3.53 kΩ121.1 kΩ
13.79 kHz3.53 kΩ97.22 kΩ
100 kHz3.53 kΩ15.77 kΩ
1 MHz3.527 kΩ3.679 kΩ
10 MHz3.413 kΩ3.342 kΩ
100 MHz3.339 kΩ3.338 kΩ
1 GHz3.294 kΩ3.294 kΩ

Every point is from a run on ngspice 42 with the SKY130 tt models (141 points).

A common-gate input looks low only while its drain is held nearly still.

The stage on its bench

A common-gate stage on its benchThe gate sits at a fixed 1.2 V. The input current enters at the source; the output is the drain.
A common-gate stage on its bench++VDD1.8 VIL20 µAM1W/L = 4/0.5RL20 kΩVX0.9 VVG1.2 VIB20 µA + i_inouts0.372 Vout0.900 V
  1. The bias

    IB pulls 20 µA out of the source and IL pushes 20 µA into the drain, so M1 carries 20 µA and RL carries none. The source settles at 0.372 V, one VGS below the gate.

    20 µA

  2. A signal current arrives

    An extra current iin leaves the source through IB. The source must fall a little to raise VGS and let M1 carry it.

    iin

  3. It leaves at the drain

    IL is fixed, so the extra current in M1 must come from RL. The same iin flows through the load: the stage passes the current on.

    iin

Read the circuit as text
  • IL current source (20 µA): + → VDD, − → out
  • M1 NMOS transistor (W/L = 4/0.5): gate → n1, drain → out, source → s
  • RL resistor (20 kΩ): pin 1 → out, pin 2 → n2
  • VX voltage source (0.9 V): + → n2, − → 0
  • VG voltage source (1.2 V): + → n1, − → 0
  • IB current source (20 µA + i_in): + → s, − → 0
  • out port: terminal → out
  • s = 0.372 V
  • out = 0.900 V

M1's body is at ground (the fourth node, 0, in the netlist). VX holds the far end of RL at 0.9 V, so the drain sits at 0.9 V for every RL.

In a common-gate stage the gate is held at a fixed DC voltage, so it carries no signal: it is AC ground. The input drives the source and the output is taken at the drain.

The bench keeps the bias the same for every load. An ideal 20 µA source feeds the drain, and the load resistance RL returns to 0.9 V, so RL carries no DC current. Only the small-signal load changes from copy to copy.

To read the input resistance, the input source carries a 1 A AC test current as well as its 20 µA. Small-signal analysis is linear, so the source voltage in volts is then Rin in ohms.

A low input resistance

Push the source up by a small voltage v. VGS falls by v, and so does VBS, because the body sits at ground. The current falls by (gm + gmb)·v. So, to first order, Rin = 1/(gm + gmb).

The lab prints gm = 252.1 µS and gmb = 46.01 µS, so 1/(gm + gmb) = 3354 Ω. With RL = 20 kΩ the run measures 3530 Ω. Two effects make up the 176 Ω gap.

The first is the drain. The signal current flows through RL and lifts the drain, and through ro that pushes current back toward the source. Solve the node equations and Rin = (ro + RL)/(1 + (gm + gmb)·ro), with ro = 1/gds = 347 kΩ. That gives 3513 Ω. The second is the 16 Ω of source diffusion in the model, met in E3.5.

RLRin measured1/(gm + gmb)Full formula
20 kΩrin_20k = 3.529678e+033354 Ωrin_ex_20k = 3.513220e+03
200 kΩrin_200k = 5.250956e+033354 Ωrin_ex_200k = 5.234497e+03
2 MΩrin_2meg = 2.246378e+043354 Ωrin_ex_2meg = 2.244728e+04
20 MΩrin_20meg = 1.945957e+053354 Ωrin_ex_20meg = 1.945751e+05

All four at the same bias (20 µA, drain at 0.9 V). The full formula misses each measurement by the same 16-21 Ω of source diffusion.

Read the formula at its two ends. While RL ≪ ro, the input is about 1/(gm + gmb), a few kilohms. Once RL reaches ro or beyond, Rin grows with RL, roughly RL/((gm + gmb)·ro). Here (gm + gmb)·ro = 104, so 20 MΩ of load shows up as 195 kΩ at the input.

A current buffer

The input current has only one way out: through M1 to the drain. IB and IL are ideal sources, so they take no signal current. Every bit of iin reaches the load, a current gain of 1.

So the common gate is a current buffer. It takes a current at a low resistance and delivers the same current at a high resistance. A sensor that delivers a current, or a transistor whose drain must be held still, can drive it.

Drive the source with a voltage instead, and the drain moves the same way: a non-inverting voltage gain. To first order it is (gm + gmb)·RL = 5.96. The lab measures 5.67, and the full form (1 + (gm + gmb)·ro)·RL/(ro + RL) gives 5.69. The gain is that of a common-source stage, but the input resistance is low.

Asked in interviews

  1. What is the input resistance of a common-gate stage?

    About 1/(gm + gmb) when the drain load is much smaller than ro: 3.35 kΩ for W/L = 4/0.5 µm at 20 µA. The full form is (ro + RL)/(1 + (gm + gmb)·ro).

  2. Why does it depend on the load?

    The signal current lifts the drain by i·RL, and ro couples that back to the source. With a load near ro or above, Rin grows roughly as RL/((gm + gmb)·ro): 195 kΩ for a 20 MΩ load here.

  3. What is a current buffer, and where is it used?

    A stage with current gain near 1, low input resistance and high output resistance. The common gate is one: it is the top device of a cascode and the input of current-mode circuits.

Try it

One op reads gm, gmb and gds of M1; all four copies share that bias. The ac run then reads each source voltage, which is Rin in ohms, and computes both formulas from the printed parameters with let.

Predict before each change. Lower VG to 1.0 V: the source drops, but the current is still 20 µA, so Rin barely moves. Add CL4 o4 0 1p and sweep to 1 GHz: the 20 MΩ copy's Rin falls toward 3.35 kΩ, as in the hook. Add nrs=0 to XM1: rin_20k meets rin_ex_20k.

SPICEngspice 42 · simulator service
Edit the netlist, then run it

        
Expected measurements: vs_dc = 3.715351e-01 gm = 2.521392e-04 gmb = 4.600871e-05 gds = 2.878613e-06 rin_simple = 3.354040e+03 rin_20k = 3.529678e+03 rin_ex_20k = 3.513220e+03 rin_200k = 5.250956e+03 rin_ex_200k = 5.234497e+03 rin_2meg = 2.246378e+04 rin_ex_2meg = 2.244728e+04 rin_20meg = 1.945957e+05 rin_ex_20meg = 1.945751e+05 gain_20k = 5.666240e+00 gain_ex_20k = 5.692784e+00



        
      

    
Check yourself

      

        
Predict the outputThis is the lab's 20 kΩ copy alone. The 1 A AC test current enters at the source. Type the line meas prints for the AC drain voltage (format: vout = 6.319360e-01).
      
* the lab's 20 k common-gate stage: the AC drain voltage for 1 A into the source
.lib sky130 tt
VDD vdd 0 1.8
VG vg 0 1.2
VX vx 0 0.9
IB1 s1 0 dc 20u ac 1
XM1 o1 vg s1 0 sky130_fd_pr__nfet_01v8 W=4 L=0.5
IL1 vdd o1 20u
RL1 o1 vx 20k
.control
ac dec 10 100 10k
meas ac vout FIND vm(o1) AT=100
.endc
.end


      

      

      


ConceptRead the hook plot. Above about which frequency do both loads give nearly the same input resistance?


ConceptA common-gate stage has gm + gmb = 300 µS and a drain load much smaller than ro. About what is its input resistance?


ConceptOn the bench, with the bias held at 20 µA, why does Rin rise when RL grows from 20 kΩ to 20 MΩ?


ConceptWhich line does NOT make a common-gate stage with its input at s, output at o and gate bias vg? Nodes are drain, gate, source, body.

        

        
      

    

    
Remember
  • A common-gate stage holds its gate at AC ground, takes the input at the source and the output at the drain.
  • Its input resistance is about 1/(gm + gmb), a few kilohms, only while the drain load is much smaller than ro.
  • The full form (ro + RL)/(1 + (gm + gmb)·ro) grows with the load: a 20 MΩ load gives 195 kΩ here.
  • Every signal current that enters the source leaves at the drain: a current buffer, and the top half of a cascode.