Phase margin and the step response

Phase margin

A negative-feedback loop subtracts what comes back from what goes in. The loop gain T carries phase shift, and every pole delays the returning signal a little more as the frequency rises. At the frequency where the delay reaches a half-cycle, −180°, the subtraction turns into an addition.

If |T| is still 1 or more there, a signal that goes once around comes back as large as it left, with the same sign. It feeds itself and the loop oscillates. So the place to look is the unity-gain frequency f_u, where |T| = 1. The phase margin is how far the phase there is from −180°: PM = 180° + ∠T(f_u).

To measure T, open the loop for the AC signal and keep it closed for DC, so the bias stays right. The lab uses the bench of E5: 1 TH from the output to M1's gate and 1 F from that gate to ground. In a buffer the output drives that gate directly, and a gate draws almost no current, so the break changes almost nothing. E6.5 shows when this simple break lies and how to measure T without breaking the loop at all.

Phase margin in the step response

Now close the loop and step it. Five buffers, one per compensation, get the same 10 mV step. The step is small on purpose: the circuit stays linear, and no transistor runs out of current (E5.6 shows what a large step does).

Name the link. With one dominant pole and one second pole, the closed loop behaves like a second-order system with a damping ratio ζ. Then PM = atan(2ζ/√(√(1 + 4ζ^{4}) − 2ζ^{2})), and the overshoot of a step is e^{−πζ/√(1 − ζ^{2})}. Solve the first for ζ and put it into the second.

The formula tracks every measurement within 3.3 points. The real loop has more than two poles and a zero, so it is a model, and a good one. Two rules follow. About 45° rings by about 23 %; 60° overshoots about 9 %. And more margin is not always faster: the 74.5° loop never overshoots, yet settles later than the 60° one. That is why 60-70° is the usual design target.

Why the buffer is the hardest loop

In a buffer the feedback factor is β = 1, so T = A: all of the op-amp's gain goes around the loop. Then |T| crosses 1 at the op-amp's own f_u, as high as it can be, where the second pole has added the most lag.

Wire the same op-amp, still with 1 pF alone, as a gain-of-two amplifier with 200 kΩ resistors. Now β = 0.5, |T| reaches 1 at 11.3 MHz instead of 20.8 MHz, and the phase there is −142.6°. The margin rises from 27.3° to 37.4° with no change to the op-amp. A smaller β only moves the crossover down, so the buffer is the case to design for.

This loop is opened between the output and the resistors. Opened at M1's gate, as the buffer was, it reads 52.1°, and that is too high. The gate is now fed through 100 kΩ, and its own capacitance makes a pole there that the gate break removes. A step decides: the same amplifier overshoots by 34.6 %, near the 32 % the second-order relation gives for 37.4° and far from the 16 % it gives for 52.1°. E6.5 measures the difference and shows how to measure T without opening the loop.

Take the compensation away and the margin goes below zero, to −14.9° at f_u = 66.2 MHz, and the step no longer settles at all.

.param cc=1p rz=0

.param cc=1p rz=5k

Try it

Run the netlist: the ac analysis gives fu and pm on the open-loop bench, and the tran analysis gives the overshoot (in % of the step) and the time the output last leaves the 1 % band. Open Plots for the loop gain and the step.

Now edit the .param line. Try cc=2p rz=0, then cc=1p rz=5k, then cc=1p rz=10k, and pair each pm with its overshoot before you look at the table above. Last, set cc=0.5p rz=0 and predict the overshoot from the second-order formula first.

Check yourself

* an ideal amplifier of gain 2000 in a gain-of-two loop, opened at its - input by 1 TH and 1 F
VIN in 0 dc 0 ac 1
E1 out 0 in inn 2000
RF out tap 1k
RG tap 0 1k
LB tap inn 1T
CB inn 0 1
.control
ac lin 3 10 30
meas ac t0 FIND vm(tap) AT=10
.endc
.end