Your RTL in real cells

Map RTL to the cells of a real library, read the netlist that physical design starts from, and turn levels of logic into area in µm² and delay in ns.

Lesson: L1.3
Time: 25 min
Runs on: OpenROAD
Check: 5 questions

In R4.6 four cuts of one datapath measured 29, 23, 26 and 21 levels of logic, and cut D won. Here the same four cuts are mapped to sky130_fd_sc_hd cells and timed in nanoseconds.

Measured sweepSetup slack at a 5 ns clock against R4.6's levels of logicEach point is one cut: D, B, C and A from left to right. Inputs arrive at the clock edge; no wires, an ideal clock.

Levels of logic in R4.6 21worst setup slack = 1.69 ns
Cut D, the register inside the multiply: 21 levels, slack 1.6897 ns. It needs a clock of 3.3103 ns or more.
Levels of logic in R4.6 23worst setup slack = 596.6 ps
Cut B, the register after a + b: 23 levels, slack 0.5966 ns. It needs a clock of 4.4034 ns or more.
Levels of logic in R4.6 26worst setup slack = 480.9 ps
Cut C, the register after the multiply: 26 levels, slack 0.4809 ns. It needs a clock of 4.5191 ns or more.
Levels of logic in R4.6 29worst setup slack = -105.5 ps
Cut A, the register at the output: 29 levels, slack -0.1055 ns. It needs a clock of 5.1055 ns or more.

Read the plot as a table

Levels of logic in R4.6	worst setup slack
21	1.69 ns
22	1.143 ns
23	596.6 ps
24	558 ps
25	519.5 ps
26	480.9 ps
27	285.4 ps
28	89.97 ps
29	-105.5 ps

One OpenSTA 3.1.0 run of all four cuts, a path group per cut, sky130_fd_sc_hd tt library.

The order held: D is the fastest and A the slowest. The gaps did not: three levels between B and C are worth 0.1157 ns, and two between D and B 1.0931 ns.

What synthesis hands to physical design

Physical design starts from a netlist of real library cells. The Yosys run behind R4.6's Gates tab stops at generic gates, which have no delays, so levels were the only timing number it had. Mapping each cut to sky130_fd_sc_hd takes four more steps:

Flops: dfflibmap
Each register bit becomes a library flop. These registers have an active-low asynchronous reset, so every bit becomes a dfrtp_1, 25.0240 µm² each.
Logic: abc -liberty
ABC reads each cell's function and area from the Liberty file and covers the logic with real gates. Some cells absorb several generic gates.
Constants: hilomap
An output that never changes is tied to a tie cell, conb_1, with outputs HI and LO. Cut A's y[13] is always 0: the largest result, 5865, fits in 13 bits.
Buses: splitnets
Each bus becomes one wire per bit, such as r[11], so the layout tools can name every wire they place and route.

The flow also passes a do-not-use list: cells the mapper must avoid. Here those are the low-power lpflow cells and the probe cells, as in the platform's own settings. The result is plain Verilog, one line per cell instance:

Four of the 151 instances in cut A's netlist: a cell type, an instance name and named pin connections.

sky130_fd_sc_hd__maj3_1 _170_ (.A(_078_), .B(_084_), .C(_085_), .X(_089_));
sky130_fd_sc_hd__xnor3_1 _166_ (.A(_078_), .B(_084_), .C(_085_), .X(_086_));
sky130_fd_sc_hd__dfrtp_1 _235_ (.CLK(clk), .D(\r[11] ), .Q(\r_q[11] ), .RESET_B(rst_n));
sky130_fd_sc_hd__conb_1 _261_ (.LO(y[13]));

The first two lines are one full adder. maj3_1 outputs the majority of its three inputs, which is the carry. xnor3_1 on the same three inputs gives the sum, inverted. The platform ships an adder map that would use the library's fa_1 instead, and this script does not apply it.

Area is the sum of cell areas

From now on cell area means the sum of the Liberty area of every instance. It is what a block costs in silicon before any wires or spacing.

Cut	Generic cells (R4.6)	sky130 cells	Flops	Cell area	Flops' share
A	199	151	26	1835.5104 µm²	35.4 %
B	202	145	30	1750.4288 µm²	42.9 %
C	215	174	35	1923.0944 µm²	45.5 %
D	208	170	40	1960.6304 µm²	51.1 %

Cell counts from the mapped netlists; areas are the sum of each instance's area in the pinned tt Liberty.

Two things change from R4.6. Cell counts drop by 18 to 28 %, because one library cell does the work of several generic gates. And flops weigh heavily: cut D's 40 flops are 1000.9600 µm², 51.1 % of the block. R4.6's "pipelining costs flops" is now a number: cut D pays 125.1200 µm² more than cut A to run 1.7952 ns faster.

Counts still mislead. Cut C has 174 cells and cut D 170, yet D is the larger by 37.5360 µm², because it has 5 more flops.

From levels to nanoseconds

A level of logic is one gate on the longest path. R4.6 counted 29 generic gates on cut A's; mapped, its slowest path has 15 cells, because one library cell can replace several generic gates. And real cells are not equal. The figure is that path, read from OpenSTA's report.

Timing pathThe longest path of cut A, from an input to a flop15 cells from b[0] to the D pin of A_ff235, no wires and an ideal clock.

b[0] → A_ff235setup check, latest arrival15 cells

Clock latency
Cell delay
Setup time

Step 1
The input arrives at the clock edge, at 0 ns: the constraints say it has no delay before the block.
Step 2
15 cell delays add up to the arrival, 4.9820 ns. The slowest is a maj3_1 at 0.4277 ns, the fastest a nand2_1 at 0.0653 ns.
Step 3
The capturing dfrtp_1 needs the data 0.1235 ns before the next edge: its setup time.
Step 4
4.8765 ns required minus 4.9820 ns arrived: slack -0.1055 ns. Cut A misses a 5 ns clock.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 5.0000 ns, latency 0.0000 ns, library setup time −0.1235 ns.

Arrival 4.9820 ns, required 4.8765 ns, slack −0.1055 ns (violated).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
	`b[0]` → `A_224_/B`	wire b[0]	fall	0.0000	0.0000	0.0000
1	`A_224_/B` → `A_224_/Y`	nand2_1	rise	0.0653	0.0653	0.0764
	`A_224_/Y` → `A_135_/A1`	wire A_058_	rise	0.0000	0.0653	0.0764
2	`A_135_/A1` → `A_135_/Y`	o21ai_0	fall	0.1302	0.1955	0.1149
	`A_135_/Y` → `A_141_/C`	wire A_061_	fall	0.0000	0.1955	0.1149
3	`A_141_/C` → `A_141_/X`	maj3_1	fall	0.4274	0.6229	0.1160
	`A_141_/X` → `A_143_/C`	wire A_063_	fall	0.0000	0.6229	0.1160
4	`A_143_/C` → `A_143_/X`	maj3_1	fall	0.4277	1.0506	0.1160
	`A_143_/X` → `A_145_/C`	wire A_065_	fall	0.0000	1.0506	0.1160
5	`A_145_/C` → `A_145_/X`	maj3_1	fall	0.4277	1.4783	0.1160
	`A_145_/X` → `A_148_/C`	wire A_067_	fall	0.0000	1.4783	0.1160
6	`A_148_/C` → `A_148_/X`	maj3_1	fall	0.4277	1.9060	0.1160
	`A_148_/X` → `A_156_/B`	wire A_069_	fall	0.0000	1.9060	0.1160
7	`A_156_/B` → `A_156_/X`	xnor3_1	fall	0.3797	2.2856	0.0884
	`A_156_/X` → `A_190_/A`	wire A_077_	fall	0.0000	2.2856	0.0884
8	`A_190_/A` → `A_190_/X`	xor3_1	rise	0.4152	2.7009	0.0985
	`A_190_/X` → `A_203_/C`	wire A_108_	rise	0.0000	2.7009	0.0985
9	`A_203_/C` → `A_203_/X`	xnor3_1	fall	0.2451	2.9460	0.0903
	`A_203_/X` → `A_233_/B`	wire A_008_	fall	0.0000	2.9460	0.0903
10	`A_233_/B` → `A_233_/X`	maj3_1	fall	0.3712	3.3172	0.0917
	`A_233_/X` → `A_114_/C`	wire A_036_	fall	0.0000	3.3172	0.0917
11	`A_114_/C` → `A_114_/X`	maj3_1	fall	0.3911	3.7084	0.0910
	`A_114_/X` → `A_116_/C`	wire A_038_	fall	0.0000	3.7084	0.0910
12	`A_116_/C` → `A_116_/X`	maj3_1	fall	0.3918	4.1002	0.0919
	`A_116_/X` → `A_118_/C`	wire A_040_	fall	0.0000	4.1002	0.0919
13	`A_118_/C` → `A_118_/X`	maj3_1	fall	0.4030	4.5032	0.1003
	`A_118_/X` → `A_123_/B`	wire A_042_	fall	0.0000	4.5032	0.1003
14	`A_123_/B` → `A_123_/X`	maj3_1	fall	0.3535	4.8567	0.0761
	`A_123_/X` → `A_125_/B`	wire A_046_	fall	0.0000	4.8567	0.0761
15	`A_125_/B` → `A_125_/Y`	xnor2_1	fall	0.1254	4.9820	0.0425
	`A_125_/Y` → `A_ff235/D`	wire A_r[11]	fall	0.0000	4.9820	0.0425

The report

Startpoint: b[0] (input port clocked by clk)
Endpoint: A_ff235 (rising edge-triggered flip-flop clocked by clk)
Path Group: gA
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.0000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                              0.0000    0.0000 v input external delay
    10    0.0328    0.0000    0.0000    0.0000 v b[0] (in)
                                                 b[0] (net)
                    0.0000    0.0000    0.0000 v A_224_/B (sky130_fd_sc_hd__nand2_1)
     2    0.0065    0.0764    0.0653    0.0653 ^ A_224_/Y (sky130_fd_sc_hd__nand2_1)
                                                 A_058_ (net)
                    0.0764    0.0000    0.0653 ^ A_135_/A1 (sky130_fd_sc_hd__o21ai_0)
     2    0.0073    0.1149    0.1302    0.1955 v A_135_/Y (sky130_fd_sc_hd__o21ai_0)
                                                 A_061_ (net)
                    0.1149    0.0000    0.1955 v A_141_/C (sky130_fd_sc_hd__maj3_1)
     3    0.0124    0.1160    0.4274    0.6229 v A_141_/X (sky130_fd_sc_hd__maj3_1)
                                                 A_063_ (net)
                    0.1160    0.0000    0.6229 v A_143_/C (sky130_fd_sc_hd__maj3_1)
     3    0.0124    0.1160    0.4277    1.0506 v A_143_/X (sky130_fd_sc_hd__maj3_1)
                                                 A_065_ (net)
                    0.1160    0.0000    1.0506 v A_145_/C (sky130_fd_sc_hd__maj3_1)
     3    0.0124    0.1160    0.4277    1.4783 v A_145_/X (sky130_fd_sc_hd__maj3_1)
                                                 A_067_ (net)
                    0.1160    0.0000    1.4783 v A_148_/C (sky130_fd_sc_hd__maj3_1)
     3    0.0124    0.1160    0.4277    1.9060 v A_148_/X (sky130_fd_sc_hd__maj3_1)
                                                 A_069_ (net)
                    0.1160    0.0000    1.9060 v A_156_/B (sky130_fd_sc_hd__xnor3_1)
     2    0.0066    0.0884    0.3797    2.2856 v A_156_/X (sky130_fd_sc_hd__xnor3_1)
                                                 A_077_ (net)
                    0.0884    0.0000    2.2856 v A_190_/A (sky130_fd_sc_hd__xor3_1)
     2    0.0067    0.0985    0.4152    2.7009 ^ A_190_/X (sky130_fd_sc_hd__xor3_1)
                                                 A_108_ (net)
                    0.0985    0.0000    2.7009 ^ A_203_/C (sky130_fd_sc_hd__xnor3_1)
     2    0.0069    0.0903    0.2451    2.9460 v A_203_/X (sky130_fd_sc_hd__xnor3_1)
                                                 A_008_ (net)
                    0.0903    0.0000    2.9460 v A_233_/B (sky130_fd_sc_hd__maj3_1)
     2    0.0073    0.0917    0.3712    3.3172 v A_233_/X (sky130_fd_sc_hd__maj3_1)
                                                 A_036_ (net)
                    0.0917    0.0000    3.3172 v A_114_/C (sky130_fd_sc_hd__maj3_1)
     2    0.0072    0.0910    0.3911    3.7084 v A_114_/X (sky130_fd_sc_hd__maj3_1)
                                                 A_038_ (net)
                    0.0910    0.0000    3.7084 v A_116_/C (sky130_fd_sc_hd__maj3_1)
     2    0.0073    0.0919    0.3918    4.1002 v A_116_/X (sky130_fd_sc_hd__maj3_1)
                                                 A_040_ (net)
                    0.0919    0.0000    4.1002 v A_118_/C (sky130_fd_sc_hd__maj3_1)
     3    0.0089    0.1003    0.4030    4.5032 v A_118_/X (sky130_fd_sc_hd__maj3_1)
                                                 A_042_ (net)
                    0.1003    0.0000    4.5032 v A_123_/B (sky130_fd_sc_hd__maj3_1)
     1    0.0045    0.0761    0.3535    4.8567 v A_123_/X (sky130_fd_sc_hd__maj3_1)
                                                 A_046_ (net)
                    0.0761    0.0000    4.8567 v A_125_/B (sky130_fd_sc_hd__xnor2_1)
     1    0.0019    0.0425    0.1254    4.9820 v A_125_/Y (sky130_fd_sc_hd__xnor2_1)
                                                 A_r[11] (net)
                    0.0425    0.0000    4.9820 v A_ff235/D (sky130_fd_sc_hd__dfrtp_1)
                                        4.9820   data arrival time

                    0.0000    5.0000    5.0000   clock clk (rise edge)
                              0.0000    5.0000   clock network delay (ideal)
                              0.0000    5.0000   clock reconvergence pessimism
                                        5.0000 ^ A_ff235/CLK (sky130_fd_sc_hd__dfrtp_1)
                             -0.1235    4.8765   library setup time
                                        4.8765   data required time
-------------------------------------------------------------------------------------
                                        4.8765   data required time
                                       -4.9820   data arrival time
-------------------------------------------------------------------------------------
                                       -0.1055   slack (VIOLATED)

OpenSTA 3.1.0 on the mapped netlist, sky130_fd_sc_hd tt library.

Nine of the 15 cells are maj3_1 carries: the adders ripple. So a level is worth anything from 0.07 to 0.43 ns here, and three levels between B and C bought only 0.1157 ns. The shortest clock period, arrival plus setup, is the number to compare: A 5.1055 ns, B 4.4034 ns, C 4.5191 ns, D 3.3103 ns.

This number still leaves things out. No wire has any capacitance, the clock reaches every flop at the same instant, and every cell is typical. The flow lesson, L1.1, showed what wires and a clock tree cost. L2 explains how OpenSTA computes each delay.

Asked in interviews

What does synthesis hand to physical design?
A structural netlist of library cells: one instance per cell, named pin connections, one wire per bit, constants on tie cells, plus the constraints (SDC) the design must meet.
Why are constants mapped to tie cells?
Flows avoid wiring a gate input straight to a supply rail. A tie cell gives a driven HI or LO output instead, which the layout tools can place near its loads.
How would you estimate the area of a block before layout?
Map it to the target library and sum the cell areas, then divide by the planned utilization to get the core. Cell count alone misleads, since a flop can be five or six times a NAND.
Is "levels of logic" a timing number?
Only a proxy. Real cells differ several times in delay and load matters, so two designs a few levels apart can be close in ns. Time the mapped netlist with STA.

Try it

Time cut A alone at a 5 ns clock. Output lists the worst slack and check_setup's notes; Paths draws the slowest paths, cell by cell.

Change the period until the worst slack is just above zero. Compare it with the shortest period the plot gives for cut A.

STAOpenSTA in OpenROAD 26Q2 · sky130hd tt_025C_1v80 Liberty · simulator service

Edit the constraints, then run them

Expected: WNS -0.1055 ns

Read the netlist: chain.v

module chain (a, b, c, clk, y, rst_n);
  input [7:0] a;
  input [7:0] b;
  input [7:0] c;
  input clk;
  output [13:0] y;
  input rst_n;
  wire _000_, _001_, _002_, _003_, _004_, _005_, _006_, _007_, _008_, _009_, _010_, _011_;
  wire _012_, _013_, _014_, _015_, _016_, _017_, _018_, _019_, _020_, _021_, _022_, _023_;
  wire _024_, _025_, _026_, _027_, _028_, _029_, _030_, _031_, _032_, _033_, _034_, _035_;
  wire _036_, _037_, _038_, _039_, _040_, _041_, _042_, _043_, _044_, _045_, _046_, _047_;
  wire _048_, _049_, _050_, _051_, _052_, _053_, _054_, _055_, _056_, _057_, _058_, _059_;
  wire _060_, _061_, _062_, _063_, _064_, _065_, _066_, _067_, _068_, _069_, _070_, _071_;
  wire _072_, _073_, _074_, _075_, _076_, _077_, _078_, _079_, _080_, _081_, _082_, _083_;
  wire _084_, _085_, _086_, _087_, _088_, _089_, _090_, _091_, _092_, _093_, _094_, _095_;
  wire _096_, _097_, _098_, _099_, _100_, _101_, _102_, _103_, _104_, _105_, _106_, _107_;
  wire _108_, _109_, _110_;
  wire \r[0] ;
  wire \r[10] ;
  wire \r[11] ;
  wire \r[12] ;
  wire \r[1] ;
  wire \r[2] ;
  wire \r[3] ;
  wire \r[4] ;
  wire \r[5] ;
  wire \r[6] ;
  wire \r[7] ;
  wire \r[8] ;
  wire \r[9] ;
  wire \r_q[0] ;
  wire \r_q[10] ;
  wire \r_q[11] ;
  wire \r_q[12] ;
  wire \r_q[1] ;
  wire \r_q[2] ;
  wire \r_q[3] ;
  wire \r_q[4] ;
  wire \r_q[5] ;
  wire \r_q[6] ;
  wire \r_q[7] ;
  wire \r_q[8] ;
  wire \r_q[9] ;
  sky130_fd_sc_hd__clkinv_1 _111_ (.A(c[7]), .Y(_049_));
  sky130_fd_sc_hd__clkinv_1 _112_ (.A(c[6]), .Y(_050_));
  sky130_fd_sc_hd__nor2_1 _113_ (.A(a[1]), .B(b[1]), .Y(_059_));
  sky130_fd_sc_hd__maj3_1 _114_ (.A(_109_), .B(_110_), .C(_036_), .X(_038_));
  sky130_fd_sc_hd__xnor2_1 _115_ (.A(_099_), .B(_101_), .Y(_039_));
  sky130_fd_sc_hd__maj3_1 _116_ (.A(_100_), .B(_101_), .C(_038_), .X(_040_));
  sky130_fd_sc_hd__xor2_1 _117_ (.A(_087_), .B(_092_), .X(_041_));
  sky130_fd_sc_hd__maj3_1 _118_ (.A(_088_), .B(_092_), .C(_040_), .X(_042_));
  sky130_fd_sc_hd__o22ai_1 _119_ (.A1(_055_), .A2(_075_), .B1(_076_), .B2(_083_), .Y(_043_));
  sky130_fd_sc_hd__xor2_1 _120_ (.A(_091_), .B(_043_), .X(_044_));
  sky130_fd_sc_hd__nand2_1 _121_ (.A(_042_), .B(_044_), .Y(_045_));
  sky130_fd_sc_hd__a21boi_0 _122_ (.A1(_075_), .A2(_045_), .B1_N(_074_), .Y(\r[12] ));
  sky130_fd_sc_hd__maj3_1 _123_ (.A(_091_), .B(_042_), .C(_043_), .X(_046_));
  sky130_fd_sc_hd__xor2_1 _124_ (.A(a[1]), .B(b[1]), .X(_060_));
  sky130_fd_sc_hd__xnor2_1 _125_ (.A(_083_), .B(_046_), .Y(\r[11] ));
  sky130_fd_sc_hd__xor2_1 _126_ (.A(_042_), .B(_044_), .X(\r[10] ));
  sky130_fd_sc_hd__xnor2_1 _127_ (.A(_040_), .B(_041_), .Y(\r[9] ));
  sky130_fd_sc_hd__xor2_1 _128_ (.A(_038_), .B(_039_), .X(\r[8] ));
  sky130_fd_sc_hd__xnor2_1 _129_ (.A(_036_), .B(_037_), .Y(\r[7] ));
  sky130_fd_sc_hd__xnor2_1 _130_ (.A(_034_), .B(_035_), .Y(\r[6] ));
  sky130_fd_sc_hd__xnor2_1 _131_ (.A(_032_), .B(_033_), .Y(\r[5] ));
  sky130_fd_sc_hd__xnor2_1 _132_ (.A(_030_), .B(_031_), .Y(\r[4] ));
  sky130_fd_sc_hd__nand2_1 _133_ (.A(_019_), .B(_029_), .Y(_047_));
  sky130_fd_sc_hd__xnor2_1 _134_ (.A(_025_), .B(_047_), .Y(\r[3] ));
  sky130_fd_sc_hd__o21ai_0 _135_ (.A1(_058_), .A2(_059_), .B1(_057_), .Y(_061_));
  sky130_fd_sc_hd__xnor2_1 _136_ (.A(_027_), .B(_028_), .Y(\r[2] ));
  sky130_fd_sc_hd__nor2_1 _137_ (.A(c[0]), .B(_020_), .Y(_048_));
  sky130_fd_sc_hd__xnor2_1 _138_ (.A(_026_), .B(_048_), .Y(\r[1] ));
  sky130_fd_sc_hd__xnor2_1 _139_ (.A(c[0]), .B(_020_), .Y(\r[0] ));
  sky130_fd_sc_hd__xor2_1 _140_ (.A(a[2]), .B(b[2]), .X(_062_));
  sky130_fd_sc_hd__maj3_1 _141_ (.A(a[2]), .B(b[2]), .C(_061_), .X(_063_));
  sky130_fd_sc_hd__xor2_1 _142_ (.A(a[3]), .B(b[3]), .X(_064_));
  sky130_fd_sc_hd__maj3_1 _143_ (.A(a[3]), .B(b[3]), .C(_063_), .X(_065_));
  sky130_fd_sc_hd__xor2_1 _144_ (.A(a[4]), .B(b[4]), .X(_066_));
  sky130_fd_sc_hd__maj3_1 _145_ (.A(a[4]), .B(b[4]), .C(_065_), .X(_067_));
  sky130_fd_sc_hd__xor2_1 _146_ (.A(a[5]), .B(b[5]), .X(_068_));
  sky130_fd_sc_hd__clkinv_1 _147_ (.A(c[5]), .Y(_051_));
  sky130_fd_sc_hd__maj3_1 _148_ (.A(a[5]), .B(b[5]), .C(_067_), .X(_069_));
  sky130_fd_sc_hd__xor2_1 _149_ (.A(a[6]), .B(b[6]), .X(_070_));
  sky130_fd_sc_hd__maj3_1 _150_ (.A(a[6]), .B(b[6]), .C(_069_), .X(_071_));
  sky130_fd_sc_hd__nor2_1 _151_ (.A(a[7]), .B(b[7]), .Y(_072_));
  sky130_fd_sc_hd__nor2_1 _152_ (.A(_055_), .B(_072_), .Y(_073_));
  sky130_fd_sc_hd__a21o_1 _153_ (.A1(_071_), .A2(_073_), .B1(_055_), .X(_074_));
  sky130_fd_sc_hd__xnor2_1 _154_ (.A(_071_), .B(_073_), .Y(_075_));
  sky130_fd_sc_hd__xnor2_1 _155_ (.A(_069_), .B(_070_), .Y(_076_));
  sky130_fd_sc_hd__xnor3_1 _156_ (.A(_050_), .B(_069_), .C(_070_), .X(_077_));
  sky130_fd_sc_hd__xnor2_1 _157_ (.A(_067_), .B(_068_), .Y(_078_));
  sky130_fd_sc_hd__clkinv_1 _158_ (.A(c[4]), .Y(_052_));
  sky130_fd_sc_hd__maj3_1 _159_ (.A(_050_), .B(_076_), .C(_078_), .X(_079_));
  sky130_fd_sc_hd__xnor3_1 _160_ (.A(_049_), .B(_071_), .C(_073_), .X(_080_));
  sky130_fd_sc_hd__xnor2_1 _161_ (.A(_076_), .B(_080_), .Y(_081_));
  sky130_fd_sc_hd__nor2b_1 _162_ (.A(_079_), .B_N(_081_), .Y(_082_));
  sky130_fd_sc_hd__nand2_1 _163_ (.A(_074_), .B(_075_), .Y(_083_));
  sky130_fd_sc_hd__mux2i_1 _164_ (.A0(_056_), .A1(_074_), .S(_075_), .Y(_084_));
  sky130_fd_sc_hd__maj3_1 _165_ (.A(_049_), .B(_075_), .C(_076_), .X(_085_));
  sky130_fd_sc_hd__xnor3_1 _166_ (.A(_078_), .B(_084_), .C(_085_), .X(_086_));
  sky130_fd_sc_hd__nand2_1 _167_ (.A(_082_), .B(_086_), .Y(_087_));
  sky130_fd_sc_hd__clkinv_1 _168_ (.A(_087_), .Y(_088_));
  sky130_fd_sc_hd__clkinv_1 _169_ (.A(c[3]), .Y(_053_));
  sky130_fd_sc_hd__maj3_1 _170_ (.A(_078_), .B(_084_), .C(_085_), .X(_089_));
  sky130_fd_sc_hd__xnor2_1 _171_ (.A(_076_), .B(_083_), .Y(_090_));
  sky130_fd_sc_hd__nor2_1 _172_ (.A(_089_), .B(_090_), .Y(_091_));
  sky130_fd_sc_hd__xor2_1 _173_ (.A(_089_), .B(_090_), .X(_092_));
  sky130_fd_sc_hd__xnor3_1 _174_ (.A(_051_), .B(_067_), .C(_068_), .X(_093_));
  sky130_fd_sc_hd__xnor2_1 _175_ (.A(_065_), .B(_066_), .Y(_094_));
  sky130_fd_sc_hd__maj3_1 _176_ (.A(_051_), .B(_078_), .C(_094_), .X(_095_));
  sky130_fd_sc_hd__xnor2_1 _177_ (.A(_077_), .B(_078_), .Y(_096_));
  sky130_fd_sc_hd__nand2b_1 _178_ (.A_N(_095_), .B(_096_), .Y(_097_));
  sky130_fd_sc_hd__xnor3_1 _179_ (.A(_076_), .B(_079_), .C(_080_), .X(_098_));
  sky130_fd_sc_hd__clkinv_1 _180_ (.A(c[2]), .Y(_054_));
  sky130_fd_sc_hd__maj3_1 _181_ (.A(_094_), .B(_097_), .C(_098_), .X(_099_));
  sky130_fd_sc_hd__clkinv_1 _182_ (.A(_099_), .Y(_100_));
  sky130_fd_sc_hd__xor2_1 _183_ (.A(_082_), .B(_086_), .X(_101_));
  sky130_fd_sc_hd__xnor3_1 _184_ (.A(_052_), .B(_065_), .C(_066_), .X(_102_));
  sky130_fd_sc_hd__xnor2_1 _185_ (.A(_063_), .B(_064_), .Y(_103_));
  sky130_fd_sc_hd__clkinv_1 _186_ (.A(_103_), .Y(_104_));
  sky130_fd_sc_hd__maj3_1 _187_ (.A(_052_), .B(_094_), .C(_103_), .X(_105_));
  sky130_fd_sc_hd__xor2_1 _188_ (.A(_093_), .B(_094_), .X(_106_));
  sky130_fd_sc_hd__nor2_1 _189_ (.A(_105_), .B(_106_), .Y(_107_));
  sky130_fd_sc_hd__xor3_1 _190_ (.A(_077_), .B(_078_), .C(_095_), .X(_108_));
  sky130_fd_sc_hd__and2_0 _191_ (.A(a[7]), .B(b[7]), .X(_055_));
  sky130_fd_sc_hd__maj3_1 _192_ (.A(_104_), .B(_107_), .C(_108_), .X(_109_));
  sky130_fd_sc_hd__xnor3_1 _193_ (.A(_094_), .B(_097_), .C(_098_), .X(_110_));
  sky130_fd_sc_hd__xnor3_1 _194_ (.A(_053_), .B(_063_), .C(_064_), .X(_000_));
  sky130_fd_sc_hd__xnor2_1 _195_ (.A(_061_), .B(_062_), .Y(_001_));
  sky130_fd_sc_hd__clkinv_1 _196_ (.A(_001_), .Y(_002_));
  sky130_fd_sc_hd__maj3_1 _197_ (.A(_053_), .B(_103_), .C(_001_), .X(_003_));
  sky130_fd_sc_hd__xnor2_1 _198_ (.A(_102_), .B(_104_), .Y(_004_));
  sky130_fd_sc_hd__nor2_1 _199_ (.A(_003_), .B(_004_), .Y(_005_));
  sky130_fd_sc_hd__xor3_1 _200_ (.A(_093_), .B(_094_), .C(_105_), .X(_006_));
  sky130_fd_sc_hd__maj3_1 _201_ (.A(_002_), .B(_005_), .C(_006_), .X(_007_));
  sky130_fd_sc_hd__nand2_1 _202_ (.A(a[7]), .B(b[7]), .Y(_056_));
  sky130_fd_sc_hd__xnor3_1 _203_ (.A(_103_), .B(_107_), .C(_108_), .X(_008_));
  sky130_fd_sc_hd__xnor2_1 _204_ (.A(_058_), .B(_060_), .Y(_009_));
  sky130_fd_sc_hd__clkinv_1 _205_ (.A(_009_), .Y(_010_));
  sky130_fd_sc_hd__maj3_1 _206_ (.A(_054_), .B(_001_), .C(_010_), .X(_011_));
  sky130_fd_sc_hd__xnor2_1 _207_ (.A(_000_), .B(_002_), .Y(_012_));
  sky130_fd_sc_hd__nor2_1 _208_ (.A(_011_), .B(_012_), .Y(_013_));
  sky130_fd_sc_hd__xnor3_1 _209_ (.A(_102_), .B(_104_), .C(_003_), .X(_014_));
  sky130_fd_sc_hd__maj3_1 _210_ (.A(_009_), .B(_013_), .C(_014_), .X(_015_));
  sky130_fd_sc_hd__xnor3_1 _211_ (.A(_001_), .B(_005_), .C(_006_), .X(_016_));
  sky130_fd_sc_hd__xnor3_1 _212_ (.A(_010_), .B(_013_), .C(_014_), .X(_017_));
  sky130_fd_sc_hd__nand2_1 _213_ (.A(a[1]), .B(b[1]), .Y(_057_));
  sky130_fd_sc_hd__xnor3_1 _214_ (.A(_054_), .B(_001_), .C(_009_), .X(_018_));
  sky130_fd_sc_hd__xor2_1 _215_ (.A(a[0]), .B(b[0]), .X(_019_));
  sky130_fd_sc_hd__xnor2_1 _216_ (.A(a[0]), .B(b[0]), .Y(_020_));
  sky130_fd_sc_hd__maj3_1 _217_ (.A(c[1]), .B(_009_), .C(_019_), .X(_021_));
  sky130_fd_sc_hd__nor2b_1 _218_ (.A(_018_), .B_N(_021_), .Y(_022_));
  sky130_fd_sc_hd__xnor3_1 _219_ (.A(_000_), .B(_002_), .C(_011_), .X(_023_));
  sky130_fd_sc_hd__maj3_1 _220_ (.A(_019_), .B(_022_), .C(_023_), .X(_024_));
  sky130_fd_sc_hd__xor2_1 _221_ (.A(_022_), .B(_023_), .X(_025_));
  sky130_fd_sc_hd__xnor2_1 _222_ (.A(c[1]), .B(_009_), .Y(_026_));
  sky130_fd_sc_hd__nand3_1 _223_ (.A(c[0]), .B(_019_), .C(_026_), .Y(_027_));
  sky130_fd_sc_hd__nand2_1 _224_ (.A(a[0]), .B(b[0]), .Y(_058_));
  sky130_fd_sc_hd__xnor2_1 _225_ (.A(_018_), .B(_021_), .Y(_028_));
  sky130_fd_sc_hd__nand2b_1 _226_ (.A_N(_027_), .B(_028_), .Y(_029_));
  sky130_fd_sc_hd__nor2_1 _227_ (.A(_025_), .B(_029_), .Y(_030_));
  sky130_fd_sc_hd__xnor2_1 _228_ (.A(_017_), .B(_024_), .Y(_031_));
  sky130_fd_sc_hd__maj3_1 _229_ (.A(_017_), .B(_024_), .C(_030_), .X(_032_));
  sky130_fd_sc_hd__xnor2_1 _230_ (.A(_015_), .B(_016_), .Y(_033_));
  sky130_fd_sc_hd__maj3_1 _231_ (.A(_015_), .B(_016_), .C(_032_), .X(_034_));
  sky130_fd_sc_hd__xnor2_1 _232_ (.A(_007_), .B(_008_), .Y(_035_));
  sky130_fd_sc_hd__maj3_1 _233_ (.A(_007_), .B(_008_), .C(_034_), .X(_036_));
  sky130_fd_sc_hd__xnor2_1 _234_ (.A(_109_), .B(_110_), .Y(_037_));
  sky130_fd_sc_hd__dfrtp_1 _235_ (.CLK(clk), .D(\r[11] ), .Q(\r_q[11] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _236_ (.CLK(clk), .D(\r[12] ), .Q(\r_q[12] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _237_ (.CLK(clk), .D(\r_q[0] ), .Q(y[0]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _238_ (.CLK(clk), .D(\r_q[1] ), .Q(y[1]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _239_ (.CLK(clk), .D(\r_q[2] ), .Q(y[2]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _240_ (.CLK(clk), .D(\r_q[3] ), .Q(y[3]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _241_ (.CLK(clk), .D(\r_q[4] ), .Q(y[4]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _242_ (.CLK(clk), .D(\r_q[5] ), .Q(y[5]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _243_ (.CLK(clk), .D(\r_q[6] ), .Q(y[6]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _244_ (.CLK(clk), .D(\r_q[7] ), .Q(y[7]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _245_ (.CLK(clk), .D(\r_q[8] ), .Q(y[8]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _246_ (.CLK(clk), .D(\r_q[9] ), .Q(y[9]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _247_ (.CLK(clk), .D(\r_q[10] ), .Q(y[10]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _248_ (.CLK(clk), .D(\r_q[11] ), .Q(y[11]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _249_ (.CLK(clk), .D(\r_q[12] ), .Q(y[12]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _250_ (.CLK(clk), .D(\r[0] ), .Q(\r_q[0] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _251_ (.CLK(clk), .D(\r[1] ), .Q(\r_q[1] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _252_ (.CLK(clk), .D(\r[2] ), .Q(\r_q[2] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _253_ (.CLK(clk), .D(\r[3] ), .Q(\r_q[3] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _254_ (.CLK(clk), .D(\r[4] ), .Q(\r_q[4] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _255_ (.CLK(clk), .D(\r[5] ), .Q(\r_q[5] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _256_ (.CLK(clk), .D(\r[6] ), .Q(\r_q[6] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _257_ (.CLK(clk), .D(\r[7] ), .Q(\r_q[7] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _258_ (.CLK(clk), .D(\r[8] ), .Q(\r_q[8] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _259_ (.CLK(clk), .D(\r[9] ), .Q(\r_q[9] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _260_ (.CLK(clk), .D(\r[10] ), .Q(\r_q[10] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__conb_1 _261_ (.LO(y[13]));
endmodule

Check yourself

Predict the outputCut A has a worst setup slack of -0.1055 ns at a 5 ns clock. What worst slack does OpenSTA report at a 5.5 ns clock, in ns?

create_clock -name clk -period 5.5 [get_ports clk]
set_input_delay 0 -clock clk [delete_from_list [all_inputs] [get_ports {clk rst_n}]]

Read the netlist: design.v

module chain (a, b, c, clk, y, rst_n);
  input [7:0] a;
  input [7:0] b;
  input [7:0] c;
  input clk;
  output [13:0] y;
  input rst_n;
  wire _000_, _001_, _002_, _003_, _004_, _005_, _006_, _007_, _008_, _009_, _010_, _011_;
  wire _012_, _013_, _014_, _015_, _016_, _017_, _018_, _019_, _020_, _021_, _022_, _023_;
  wire _024_, _025_, _026_, _027_, _028_, _029_, _030_, _031_, _032_, _033_, _034_, _035_;
  wire _036_, _037_, _038_, _039_, _040_, _041_, _042_, _043_, _044_, _045_, _046_, _047_;
  wire _048_, _049_, _050_, _051_, _052_, _053_, _054_, _055_, _056_, _057_, _058_, _059_;
  wire _060_, _061_, _062_, _063_, _064_, _065_, _066_, _067_, _068_, _069_, _070_, _071_;
  wire _072_, _073_, _074_, _075_, _076_, _077_, _078_, _079_, _080_, _081_, _082_, _083_;
  wire _084_, _085_, _086_, _087_, _088_, _089_, _090_, _091_, _092_, _093_, _094_, _095_;
  wire _096_, _097_, _098_, _099_, _100_, _101_, _102_, _103_, _104_, _105_, _106_, _107_;
  wire _108_, _109_, _110_;
  wire \r[0] ;
  wire \r[10] ;
  wire \r[11] ;
  wire \r[12] ;
  wire \r[1] ;
  wire \r[2] ;
  wire \r[3] ;
  wire \r[4] ;
  wire \r[5] ;
  wire \r[6] ;
  wire \r[7] ;
  wire \r[8] ;
  wire \r[9] ;
  wire \r_q[0] ;
  wire \r_q[10] ;
  wire \r_q[11] ;
  wire \r_q[12] ;
  wire \r_q[1] ;
  wire \r_q[2] ;
  wire \r_q[3] ;
  wire \r_q[4] ;
  wire \r_q[5] ;
  wire \r_q[6] ;
  wire \r_q[7] ;
  wire \r_q[8] ;
  wire \r_q[9] ;
  sky130_fd_sc_hd__clkinv_1 _111_ (.A(c[7]), .Y(_049_));
  sky130_fd_sc_hd__clkinv_1 _112_ (.A(c[6]), .Y(_050_));
  sky130_fd_sc_hd__nor2_1 _113_ (.A(a[1]), .B(b[1]), .Y(_059_));
  sky130_fd_sc_hd__maj3_1 _114_ (.A(_109_), .B(_110_), .C(_036_), .X(_038_));
  sky130_fd_sc_hd__xnor2_1 _115_ (.A(_099_), .B(_101_), .Y(_039_));
  sky130_fd_sc_hd__maj3_1 _116_ (.A(_100_), .B(_101_), .C(_038_), .X(_040_));
  sky130_fd_sc_hd__xor2_1 _117_ (.A(_087_), .B(_092_), .X(_041_));
  sky130_fd_sc_hd__maj3_1 _118_ (.A(_088_), .B(_092_), .C(_040_), .X(_042_));
  sky130_fd_sc_hd__o22ai_1 _119_ (.A1(_055_), .A2(_075_), .B1(_076_), .B2(_083_), .Y(_043_));
  sky130_fd_sc_hd__xor2_1 _120_ (.A(_091_), .B(_043_), .X(_044_));
  sky130_fd_sc_hd__nand2_1 _121_ (.A(_042_), .B(_044_), .Y(_045_));
  sky130_fd_sc_hd__a21boi_0 _122_ (.A1(_075_), .A2(_045_), .B1_N(_074_), .Y(\r[12] ));
  sky130_fd_sc_hd__maj3_1 _123_ (.A(_091_), .B(_042_), .C(_043_), .X(_046_));
  sky130_fd_sc_hd__xor2_1 _124_ (.A(a[1]), .B(b[1]), .X(_060_));
  sky130_fd_sc_hd__xnor2_1 _125_ (.A(_083_), .B(_046_), .Y(\r[11] ));
  sky130_fd_sc_hd__xor2_1 _126_ (.A(_042_), .B(_044_), .X(\r[10] ));
  sky130_fd_sc_hd__xnor2_1 _127_ (.A(_040_), .B(_041_), .Y(\r[9] ));
  sky130_fd_sc_hd__xor2_1 _128_ (.A(_038_), .B(_039_), .X(\r[8] ));
  sky130_fd_sc_hd__xnor2_1 _129_ (.A(_036_), .B(_037_), .Y(\r[7] ));
  sky130_fd_sc_hd__xnor2_1 _130_ (.A(_034_), .B(_035_), .Y(\r[6] ));
  sky130_fd_sc_hd__xnor2_1 _131_ (.A(_032_), .B(_033_), .Y(\r[5] ));
  sky130_fd_sc_hd__xnor2_1 _132_ (.A(_030_), .B(_031_), .Y(\r[4] ));
  sky130_fd_sc_hd__nand2_1 _133_ (.A(_019_), .B(_029_), .Y(_047_));
  sky130_fd_sc_hd__xnor2_1 _134_ (.A(_025_), .B(_047_), .Y(\r[3] ));
  sky130_fd_sc_hd__o21ai_0 _135_ (.A1(_058_), .A2(_059_), .B1(_057_), .Y(_061_));
  sky130_fd_sc_hd__xnor2_1 _136_ (.A(_027_), .B(_028_), .Y(\r[2] ));
  sky130_fd_sc_hd__nor2_1 _137_ (.A(c[0]), .B(_020_), .Y(_048_));
  sky130_fd_sc_hd__xnor2_1 _138_ (.A(_026_), .B(_048_), .Y(\r[1] ));
  sky130_fd_sc_hd__xnor2_1 _139_ (.A(c[0]), .B(_020_), .Y(\r[0] ));
  sky130_fd_sc_hd__xor2_1 _140_ (.A(a[2]), .B(b[2]), .X(_062_));
  sky130_fd_sc_hd__maj3_1 _141_ (.A(a[2]), .B(b[2]), .C(_061_), .X(_063_));
  sky130_fd_sc_hd__xor2_1 _142_ (.A(a[3]), .B(b[3]), .X(_064_));
  sky130_fd_sc_hd__maj3_1 _143_ (.A(a[3]), .B(b[3]), .C(_063_), .X(_065_));
  sky130_fd_sc_hd__xor2_1 _144_ (.A(a[4]), .B(b[4]), .X(_066_));
  sky130_fd_sc_hd__maj3_1 _145_ (.A(a[4]), .B(b[4]), .C(_065_), .X(_067_));
  sky130_fd_sc_hd__xor2_1 _146_ (.A(a[5]), .B(b[5]), .X(_068_));
  sky130_fd_sc_hd__clkinv_1 _147_ (.A(c[5]), .Y(_051_));
  sky130_fd_sc_hd__maj3_1 _148_ (.A(a[5]), .B(b[5]), .C(_067_), .X(_069_));
  sky130_fd_sc_hd__xor2_1 _149_ (.A(a[6]), .B(b[6]), .X(_070_));
  sky130_fd_sc_hd__maj3_1 _150_ (.A(a[6]), .B(b[6]), .C(_069_), .X(_071_));
  sky130_fd_sc_hd__nor2_1 _151_ (.A(a[7]), .B(b[7]), .Y(_072_));
  sky130_fd_sc_hd__nor2_1 _152_ (.A(_055_), .B(_072_), .Y(_073_));
  sky130_fd_sc_hd__a21o_1 _153_ (.A1(_071_), .A2(_073_), .B1(_055_), .X(_074_));
  sky130_fd_sc_hd__xnor2_1 _154_ (.A(_071_), .B(_073_), .Y(_075_));
  sky130_fd_sc_hd__xnor2_1 _155_ (.A(_069_), .B(_070_), .Y(_076_));
  sky130_fd_sc_hd__xnor3_1 _156_ (.A(_050_), .B(_069_), .C(_070_), .X(_077_));
  sky130_fd_sc_hd__xnor2_1 _157_ (.A(_067_), .B(_068_), .Y(_078_));
  sky130_fd_sc_hd__clkinv_1 _158_ (.A(c[4]), .Y(_052_));
  sky130_fd_sc_hd__maj3_1 _159_ (.A(_050_), .B(_076_), .C(_078_), .X(_079_));
  sky130_fd_sc_hd__xnor3_1 _160_ (.A(_049_), .B(_071_), .C(_073_), .X(_080_));
  sky130_fd_sc_hd__xnor2_1 _161_ (.A(_076_), .B(_080_), .Y(_081_));
  sky130_fd_sc_hd__nor2b_1 _162_ (.A(_079_), .B_N(_081_), .Y(_082_));
  sky130_fd_sc_hd__nand2_1 _163_ (.A(_074_), .B(_075_), .Y(_083_));
  sky130_fd_sc_hd__mux2i_1 _164_ (.A0(_056_), .A1(_074_), .S(_075_), .Y(_084_));
  sky130_fd_sc_hd__maj3_1 _165_ (.A(_049_), .B(_075_), .C(_076_), .X(_085_));
  sky130_fd_sc_hd__xnor3_1 _166_ (.A(_078_), .B(_084_), .C(_085_), .X(_086_));
  sky130_fd_sc_hd__nand2_1 _167_ (.A(_082_), .B(_086_), .Y(_087_));
  sky130_fd_sc_hd__clkinv_1 _168_ (.A(_087_), .Y(_088_));
  sky130_fd_sc_hd__clkinv_1 _169_ (.A(c[3]), .Y(_053_));
  sky130_fd_sc_hd__maj3_1 _170_ (.A(_078_), .B(_084_), .C(_085_), .X(_089_));
  sky130_fd_sc_hd__xnor2_1 _171_ (.A(_076_), .B(_083_), .Y(_090_));
  sky130_fd_sc_hd__nor2_1 _172_ (.A(_089_), .B(_090_), .Y(_091_));
  sky130_fd_sc_hd__xor2_1 _173_ (.A(_089_), .B(_090_), .X(_092_));
  sky130_fd_sc_hd__xnor3_1 _174_ (.A(_051_), .B(_067_), .C(_068_), .X(_093_));
  sky130_fd_sc_hd__xnor2_1 _175_ (.A(_065_), .B(_066_), .Y(_094_));
  sky130_fd_sc_hd__maj3_1 _176_ (.A(_051_), .B(_078_), .C(_094_), .X(_095_));
  sky130_fd_sc_hd__xnor2_1 _177_ (.A(_077_), .B(_078_), .Y(_096_));
  sky130_fd_sc_hd__nand2b_1 _178_ (.A_N(_095_), .B(_096_), .Y(_097_));
  sky130_fd_sc_hd__xnor3_1 _179_ (.A(_076_), .B(_079_), .C(_080_), .X(_098_));
  sky130_fd_sc_hd__clkinv_1 _180_ (.A(c[2]), .Y(_054_));
  sky130_fd_sc_hd__maj3_1 _181_ (.A(_094_), .B(_097_), .C(_098_), .X(_099_));
  sky130_fd_sc_hd__clkinv_1 _182_ (.A(_099_), .Y(_100_));
  sky130_fd_sc_hd__xor2_1 _183_ (.A(_082_), .B(_086_), .X(_101_));
  sky130_fd_sc_hd__xnor3_1 _184_ (.A(_052_), .B(_065_), .C(_066_), .X(_102_));
  sky130_fd_sc_hd__xnor2_1 _185_ (.A(_063_), .B(_064_), .Y(_103_));
  sky130_fd_sc_hd__clkinv_1 _186_ (.A(_103_), .Y(_104_));
  sky130_fd_sc_hd__maj3_1 _187_ (.A(_052_), .B(_094_), .C(_103_), .X(_105_));
  sky130_fd_sc_hd__xor2_1 _188_ (.A(_093_), .B(_094_), .X(_106_));
  sky130_fd_sc_hd__nor2_1 _189_ (.A(_105_), .B(_106_), .Y(_107_));
  sky130_fd_sc_hd__xor3_1 _190_ (.A(_077_), .B(_078_), .C(_095_), .X(_108_));
  sky130_fd_sc_hd__and2_0 _191_ (.A(a[7]), .B(b[7]), .X(_055_));
  sky130_fd_sc_hd__maj3_1 _192_ (.A(_104_), .B(_107_), .C(_108_), .X(_109_));
  sky130_fd_sc_hd__xnor3_1 _193_ (.A(_094_), .B(_097_), .C(_098_), .X(_110_));
  sky130_fd_sc_hd__xnor3_1 _194_ (.A(_053_), .B(_063_), .C(_064_), .X(_000_));
  sky130_fd_sc_hd__xnor2_1 _195_ (.A(_061_), .B(_062_), .Y(_001_));
  sky130_fd_sc_hd__clkinv_1 _196_ (.A(_001_), .Y(_002_));
  sky130_fd_sc_hd__maj3_1 _197_ (.A(_053_), .B(_103_), .C(_001_), .X(_003_));
  sky130_fd_sc_hd__xnor2_1 _198_ (.A(_102_), .B(_104_), .Y(_004_));
  sky130_fd_sc_hd__nor2_1 _199_ (.A(_003_), .B(_004_), .Y(_005_));
  sky130_fd_sc_hd__xor3_1 _200_ (.A(_093_), .B(_094_), .C(_105_), .X(_006_));
  sky130_fd_sc_hd__maj3_1 _201_ (.A(_002_), .B(_005_), .C(_006_), .X(_007_));
  sky130_fd_sc_hd__nand2_1 _202_ (.A(a[7]), .B(b[7]), .Y(_056_));
  sky130_fd_sc_hd__xnor3_1 _203_ (.A(_103_), .B(_107_), .C(_108_), .X(_008_));
  sky130_fd_sc_hd__xnor2_1 _204_ (.A(_058_), .B(_060_), .Y(_009_));
  sky130_fd_sc_hd__clkinv_1 _205_ (.A(_009_), .Y(_010_));
  sky130_fd_sc_hd__maj3_1 _206_ (.A(_054_), .B(_001_), .C(_010_), .X(_011_));
  sky130_fd_sc_hd__xnor2_1 _207_ (.A(_000_), .B(_002_), .Y(_012_));
  sky130_fd_sc_hd__nor2_1 _208_ (.A(_011_), .B(_012_), .Y(_013_));
  sky130_fd_sc_hd__xnor3_1 _209_ (.A(_102_), .B(_104_), .C(_003_), .X(_014_));
  sky130_fd_sc_hd__maj3_1 _210_ (.A(_009_), .B(_013_), .C(_014_), .X(_015_));
  sky130_fd_sc_hd__xnor3_1 _211_ (.A(_001_), .B(_005_), .C(_006_), .X(_016_));
  sky130_fd_sc_hd__xnor3_1 _212_ (.A(_010_), .B(_013_), .C(_014_), .X(_017_));
  sky130_fd_sc_hd__nand2_1 _213_ (.A(a[1]), .B(b[1]), .Y(_057_));
  sky130_fd_sc_hd__xnor3_1 _214_ (.A(_054_), .B(_001_), .C(_009_), .X(_018_));
  sky130_fd_sc_hd__xor2_1 _215_ (.A(a[0]), .B(b[0]), .X(_019_));
  sky130_fd_sc_hd__xnor2_1 _216_ (.A(a[0]), .B(b[0]), .Y(_020_));
  sky130_fd_sc_hd__maj3_1 _217_ (.A(c[1]), .B(_009_), .C(_019_), .X(_021_));
  sky130_fd_sc_hd__nor2b_1 _218_ (.A(_018_), .B_N(_021_), .Y(_022_));
  sky130_fd_sc_hd__xnor3_1 _219_ (.A(_000_), .B(_002_), .C(_011_), .X(_023_));
  sky130_fd_sc_hd__maj3_1 _220_ (.A(_019_), .B(_022_), .C(_023_), .X(_024_));
  sky130_fd_sc_hd__xor2_1 _221_ (.A(_022_), .B(_023_), .X(_025_));
  sky130_fd_sc_hd__xnor2_1 _222_ (.A(c[1]), .B(_009_), .Y(_026_));
  sky130_fd_sc_hd__nand3_1 _223_ (.A(c[0]), .B(_019_), .C(_026_), .Y(_027_));
  sky130_fd_sc_hd__nand2_1 _224_ (.A(a[0]), .B(b[0]), .Y(_058_));
  sky130_fd_sc_hd__xnor2_1 _225_ (.A(_018_), .B(_021_), .Y(_028_));
  sky130_fd_sc_hd__nand2b_1 _226_ (.A_N(_027_), .B(_028_), .Y(_029_));
  sky130_fd_sc_hd__nor2_1 _227_ (.A(_025_), .B(_029_), .Y(_030_));
  sky130_fd_sc_hd__xnor2_1 _228_ (.A(_017_), .B(_024_), .Y(_031_));
  sky130_fd_sc_hd__maj3_1 _229_ (.A(_017_), .B(_024_), .C(_030_), .X(_032_));
  sky130_fd_sc_hd__xnor2_1 _230_ (.A(_015_), .B(_016_), .Y(_033_));
  sky130_fd_sc_hd__maj3_1 _231_ (.A(_015_), .B(_016_), .C(_032_), .X(_034_));
  sky130_fd_sc_hd__xnor2_1 _232_ (.A(_007_), .B(_008_), .Y(_035_));
  sky130_fd_sc_hd__maj3_1 _233_ (.A(_007_), .B(_008_), .C(_034_), .X(_036_));
  sky130_fd_sc_hd__xnor2_1 _234_ (.A(_109_), .B(_110_), .Y(_037_));
  sky130_fd_sc_hd__dfrtp_1 _235_ (.CLK(clk), .D(\r[11] ), .Q(\r_q[11] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _236_ (.CLK(clk), .D(\r[12] ), .Q(\r_q[12] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _237_ (.CLK(clk), .D(\r_q[0] ), .Q(y[0]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _238_ (.CLK(clk), .D(\r_q[1] ), .Q(y[1]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _239_ (.CLK(clk), .D(\r_q[2] ), .Q(y[2]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _240_ (.CLK(clk), .D(\r_q[3] ), .Q(y[3]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _241_ (.CLK(clk), .D(\r_q[4] ), .Q(y[4]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _242_ (.CLK(clk), .D(\r_q[5] ), .Q(y[5]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _243_ (.CLK(clk), .D(\r_q[6] ), .Q(y[6]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _244_ (.CLK(clk), .D(\r_q[7] ), .Q(y[7]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _245_ (.CLK(clk), .D(\r_q[8] ), .Q(y[8]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _246_ (.CLK(clk), .D(\r_q[9] ), .Q(y[9]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _247_ (.CLK(clk), .D(\r_q[10] ), .Q(y[10]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _248_ (.CLK(clk), .D(\r_q[11] ), .Q(y[11]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _249_ (.CLK(clk), .D(\r_q[12] ), .Q(y[12]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _250_ (.CLK(clk), .D(\r[0] ), .Q(\r_q[0] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _251_ (.CLK(clk), .D(\r[1] ), .Q(\r_q[1] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _252_ (.CLK(clk), .D(\r[2] ), .Q(\r_q[2] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _253_ (.CLK(clk), .D(\r[3] ), .Q(\r_q[3] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _254_ (.CLK(clk), .D(\r[4] ), .Q(\r_q[4] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _255_ (.CLK(clk), .D(\r[5] ), .Q(\r_q[5] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _256_ (.CLK(clk), .D(\r[6] ), .Q(\r_q[6] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _257_ (.CLK(clk), .D(\r[7] ), .Q(\r_q[7] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _258_ (.CLK(clk), .D(\r[8] ), .Q(\r_q[8] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _259_ (.CLK(clk), .D(\r[9] ), .Q(\r_q[9] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _260_ (.CLK(clk), .D(\r[10] ), .Q(\r_q[10] ), .RESET_B(rst_n));
  sky130_fd_sc_hd__conb_1 _261_ (.LO(y[13]));
endmodule

ConceptWhat does hilomap do in the mapping script?

It splits each bus into one wire per bitIt marks the low-power cells the mapper must avoidIt drives constant nets from a tie cell, conb_1It maps every flop with a reset to a dfrtp cell

ConceptCut C has 174 cells and cut D 170. Why is D the larger block?

Cut C shares its tie cell with the other cutsCut D's cells are placed further apartCut D uses stronger drive strengths everywhereCut D has 5 more flops, each a large cell

ConceptCuts B and C were three levels apart in R4.6. Why are their shortest periods so close in sky130 cells?

Mapped cells merge generic gates and differ in delayThe library has one delay for all cells with the same inputsCut C's extra levels sit on paths that are never timedOpenSTA rounds every cell delay to the nearest tenth of a ns

ConceptWhat does the slack of a mapped netlist with no wires still leave out?

The clock period, which only the floorplan knowsWire capacitance and the clock skew a real clock tree addsThe setup time of the capturing flopThe delay of each library cell, which needs placement first

Remember

Physical design starts from a netlist of library cells: flops by dfflibmap, logic by ABC with the Liberty, constants on tie cells, buses split into bits.
Cell area, the sum of the Liberty areas of all instances, is the measure of a block; the cell count is not.
Flops are large cells, so pipelining costs area you can now count in µm².
Levels of logic rank designs roughly; STA on the mapped netlist gives the delay in ns, still without wires or skew.