Rows, sites, tracks and the metal stack

Read a floorplan as rows of sites, explain why every other row is flipped, and name the SKY130 routing layers with their directions, pitches and resistance.

Lesson: L1.5
Time: 25 min
Runs on: OpenROAD
Check: 5 questions

You ask OpenROAD for a core 5 µm in from the die edge. It answers with a warning, [WARNING IFP-0028] Core area lower left (5.000, 5.000) snapped to (5.060, 5.440)., and the core starts there. Nothing in a floorplan may sit off its grid.

LayoutThe counter's floorplanA 50.485 µm square die; the core holds 14 rows of 87 sites.

Tap cells
Logic
Buffers and inverters
Flip-flops
Power stripes
I/O pins

Stage: Floorplan
Cell area: 347.8 µm²
Utilization: 22.8 %
Worst max slack: 3.8370 ns
Total negative max slack: 0.0000 ns
Worst min slack: 0.4594 ns

Rows and the grid
The core starts at (5.06 µm, 5.44 µm): 11 sites and 2 rows from the die corner. Tap cells sit in the rows, and power straps cross the core on met4 and met5.

Read the layout as text

modn: die 50.49 × 50.49 µm, core 40.02 × 38.08 µm, 14 rows of 2.72 µm, 11 signal pins.

Stage	Cell area	Utilization	Worst max slack	Total negative max slack	Worst min slack	Cells placed
Floorplan	347.8 µm²	22.8 %	3.8370 ns	0.0000 ns	0.4594 ns	16 tap cells; I/O pins not placed yet

Measured with OpenROAD 26Q2 on sky130hd at 20 % utilization; no logic cell is placed yet.

5.06 µm is 11 sites of 0.46 µm, and 5.44 µm is 2 rows of 2.72 µm. Every cell, row and wire in a layout snaps to a grid like this one.

Rows of sites

A site is the smallest slot a cell can take: unithd, 0.46 µm wide and 2.72 µm tall. Every sky130_fd_sc_hd cell is one site tall and a whole number of sites wide, as L1.2 showed. A row is a line of sites across the core.

This core is 14 rows of 87 sites: 40.02 µm wide and 14 × 2.72 = 38.08 µm tall. Its area, 1523.962 µm², is what utilization divides by.

The first row has orientation N (north, upright) and the second FS (flipped south: mirrored top to bottom). They alternate all the way up. Every cell carries its supply rail, VPWR, along its top edge and its ground rail, VGND, along the bottom. Flipping every other row puts two VPWR edges together, then two VGND edges, so each metal rail serves the two rows that touch it.

Row	Orientation	Bottom edge	Rail at the bottom	Rail at the top
0	`N`	5.44 µm	VGND	VPWR
1	`FS`	8.16 µm	VPWR	VGND
2	`N`	10.88 µm	VGND	VPWR
3	`FS`	13.60 µm	VPWR	VGND

The first four rows of the floorplan above. Each rail is shared by the rows above and below it.

So the met1 rails repeat every two rows. The power grid draws them as followpins, stripes that follow the rows, and ties them to the straps on the layers above.

The metal stack

Above the cells sit the routing layers. SKY130 has li1, a local interconnect used inside cells and for their pins, and five metal layers, met1 to met5. A via joins two neighbouring layers; the tech LEF names them mcon, via, via2, via3, via4.

The SKY130 routing stack, bottom to topArrows join a layer to the one above it through a via; the labels name the via layer.

Inside the cells
li1 connects transistors inside a cell and carries its signal pins. At 12.2 Ω per square it is far too resistive for long wires.
Thin metals
met1 and met2 are 0.35 µm thick with the finest pitch. They carry short local wires densely; met1 also holds the rails.
Thick metals
met3 and met4 are 0.80 µm thick with 0.047 Ω per square: longer wires, fewer tracks.
The top layer
met5 is the thickest, 1.20 µm, at 0.0285 Ω per square. With met4 it carries the power grid.

Read the diagram as text

met5: horizontal, pitch 3.40 µm, 0.0285 Ω/sq
met4: vertical, pitch 0.92 µm, 0.047 Ω/sq
met3: horizontal, pitch 0.68 µm, 0.047 Ω/sq
met2: vertical, pitch 0.46 µm, 0.125 Ω/sq
met1: horizontal, pitch 0.34 µm, 0.125 Ω/sq
li1: vertical, pitch 0.46 µm, 12.2 Ω/sq
Power grid: Straps on met4 and met5
Standard cells: Pins on li1, rails on met1

met4 → met5: via4
met3 → met4: via3
met2 → met3: via2
met1 → met2: via
li1 → met1: mcon
Power grid → met4: straps
Standard cells → li1: pins

From the pinned sky130_fd_sc_hd tech LEF. Ω/sq is ohms per square of wire.

Layer	Preferred direction	Pitch	Minimum width	Thickness	Sheet resistance
`li1`	vertical	0.46 / 0.34 µm	0.17 µm	0.10 µm	12.2 Ω/sq
`met1`	horizontal	0.34 µm	0.14 µm	0.35 µm	0.125 Ω/sq
`met2`	vertical	0.46 µm	0.14 µm	0.35 µm	0.125 Ω/sq
`met3`	horizontal	0.68 µm	0.30 µm	0.80 µm	0.047 Ω/sq
`met4`	vertical	0.92 µm	0.30 µm	0.80 µm	0.047 Ω/sq
`met5`	horizontal	3.40 µm	1.60 µm	1.20 µm	0.0285 Ω/sq

LAYER statements of the pinned tech LEF: DIRECTION, PITCH, WIDTH, THICKNESS and RESISTANCE RPERSQ.

Sheet resistance is the resistance of a square of the layer, any size of square. A wire ten squares long has ten times that. met1 has 4.4 times the sheet resistance of met5, which is why the power grid and the longest wires go high.

Each layer has a preferred direction, and the directions alternate: met1 horizontal, met2 vertical, met3 horizontal, and so on. A route turns by changing layer through a via. A wire against its layer's direction would block every track it crosses, so routers keep it short or avoid it. The straps follow the rule too: the 2 met4 straps here are vertical and the 2 met5 straps horizontal, each 1.60 µm wide.

Tracks

A track is a line on which the router may draw a wire, one set per layer, spaced at the layer's pitch. The first sits half a pitch from the die edge. Across this 50.485 µm die that gives:

Layer	Direction	Pitch	Tracks across the die
`met1`	horizontal	0.34 µm	148
`met2`	vertical	0.46 µm	110
`met3`	horizontal	0.68 µm	74
`met4`	vertical	0.92 µm	55
`met5`	horizontal	3.40 µm	15

Counted from the pitch and the die size; the run's DEF has the same counts in its TRACKS lines.

Two numbers line up on purpose. A row is 2.72 µm, exactly 8 met1 pitches, so the horizontal tracks fit each row the same way. The met2 pitch, 0.46 µm, equals the site width, so a vertical track runs over every column of sites.

Tracks are the routing supply. A region of the core offers so many tracks per layer, and the nets that cross it need some of them. L4.2 compares the two.

Asked in interviews

Why do standard cell rows flip?
Every cell has VPWR on top and VGND at the bottom. Flipping every other row makes neighbouring rows share one rail, which halves the rails and lets the wells of both rows merge.
What is a routing track?
A line on a layer, at that layer's pitch, on which the router places wires. The tracks across a region are its routing supply.
Why do metal layers alternate direction?
With each layer in one direction, horizontal and vertical wires never block each other: a route turns by changing layer through a via. It keeps tracks regular and routing predictable.
Which layers would you use for power, and why?
The top, thickest layers: their low sheet resistance keeps the voltage drop small. Here met4 and met5 carry the straps, and met1 the rails in the rows.

Try it

Run the floorplan. Layout shows the rows and straps; "Read the layout as text" lists the rows.

Set the aspect ratio to 2 and run again: the core gets taller and narrower, with more rows of fewer sites. Then raise the utilization to 40 % and watch which stage stops the run, and why: L1.6 reads that message.

FLOWOpenROAD 26Q2 · sky130hd · simulator service

Edit the constraints, then run them

Utilization (%)Aspect ratio

Expected: floorplan utilization 22.82 % floorplan instances 43

Read the netlist: modn.v

module modn (clk, rst_n, count, tc);
  input clk;
  input rst_n;
  output [7:0] count;
  output tc;
  wire _00_, _01_, _02_, _03_, _04_, _05_, _06_, _07_, _08_;
  wire _09_, _10_, _11_, _12_, _13_, _14_, _15_, _16_, _17_;
  sky130_fd_sc_hd__clkinv_1 _18_ (.A(count[0]), .Y(_00_));
  sky130_fd_sc_hd__and3_1 _19_ (.A(count[0]), .B(count[2]), .C(count[1]), .X(_08_));
  sky130_fd_sc_hd__nor2_1 _20_ (.A(_10_), .B(_14_), .Y(_05_));
  sky130_fd_sc_hd__xor2_1 _21_ (.A(count[4]), .B(_09_), .X(_04_));
  sky130_fd_sc_hd__xnor2_1 _22_ (.A(count[3]), .B(_08_), .Y(_15_));
  sky130_fd_sc_hd__nor2_1 _23_ (.A(tc), .B(_15_), .Y(_03_));
  sky130_fd_sc_hd__a21oi_1 _24_ (.A1(count[0]), .A2(count[1]), .B1(count[2]), .Y(_16_));
  sky130_fd_sc_hd__nor2_1 _25_ (.A(_08_), .B(_16_), .Y(_02_));
  sky130_fd_sc_hd__xor2_1 _26_ (.A(count[0]), .B(count[1]), .X(_01_));
  sky130_fd_sc_hd__a41oi_1 _27_ (.A1(count[6]), .A2(count[5]), .A3(count[4]), .A4(_09_), .B1(count[7]), .Y(_17_));
  sky130_fd_sc_hd__a311oi_1 _28_ (.A1(count[6]), .A2(count[7]), .A3(_10_), .B1(tc), .C1(_17_), .Y(_07_));
  sky130_fd_sc_hd__and4_1 _29_ (.A(count[0]), .B(count[3]), .C(count[2]), .D(count[1]), .X(_09_));
  sky130_fd_sc_hd__and3_1 _30_ (.A(count[5]), .B(count[4]), .C(_09_), .X(_10_));
  sky130_fd_sc_hd__and4_1 _31_ (.A(count[6]), .B(count[5]), .C(count[4]), .D(_09_), .X(_11_));
  sky130_fd_sc_hd__nor3b_1 _32_ (.A(count[5]), .B(count[4]), .C_N(count[6]), .Y(_12_));
  sky130_fd_sc_hd__and4b_1 _33_ (.A_N(count[3]), .B(count[7]), .C(_08_), .D(_12_), .X(tc));
  sky130_fd_sc_hd__a31oi_1 _34_ (.A1(count[5]), .A2(count[4]), .A3(_09_), .B1(count[6]), .Y(_13_));
  sky130_fd_sc_hd__nor3_1 _35_ (.A(_11_), .B(tc), .C(_13_), .Y(_06_));
  sky130_fd_sc_hd__a21oi_1 _36_ (.A1(count[4]), .A2(_09_), .B1(count[5]), .Y(_14_));
  sky130_fd_sc_hd__dfrtp_1 _37_ (.CLK(clk), .D(_00_), .Q(count[0]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _38_ (.CLK(clk), .D(_01_), .Q(count[1]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _39_ (.CLK(clk), .D(_02_), .Q(count[2]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _40_ (.CLK(clk), .D(_03_), .Q(count[3]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _41_ (.CLK(clk), .D(_04_), .Q(count[4]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _42_ (.CLK(clk), .D(_05_), .Q(count[5]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _43_ (.CLK(clk), .D(_06_), .Q(count[6]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _44_ (.CLK(clk), .D(_07_), .Q(count[7]), .RESET_B(rst_n));
endmodule

Check yourself

Predict the outputThe counter's core holds 14 rows of 87 sites. Its cells and tap cells add up to 347.8336 µm². What utilization does the floorplan report, in % to two decimals?

create_clock -name clk -period 5 [get_ports clk]

Read the netlist: design.v

module modn (clk, rst_n, count, tc);
  input clk;
  input rst_n;
  output [7:0] count;
  output tc;
  wire _00_, _01_, _02_, _03_, _04_, _05_, _06_, _07_, _08_;
  wire _09_, _10_, _11_, _12_, _13_, _14_, _15_, _16_, _17_;
  sky130_fd_sc_hd__clkinv_1 _18_ (.A(count[0]), .Y(_00_));
  sky130_fd_sc_hd__and3_1 _19_ (.A(count[0]), .B(count[2]), .C(count[1]), .X(_08_));
  sky130_fd_sc_hd__nor2_1 _20_ (.A(_10_), .B(_14_), .Y(_05_));
  sky130_fd_sc_hd__xor2_1 _21_ (.A(count[4]), .B(_09_), .X(_04_));
  sky130_fd_sc_hd__xnor2_1 _22_ (.A(count[3]), .B(_08_), .Y(_15_));
  sky130_fd_sc_hd__nor2_1 _23_ (.A(tc), .B(_15_), .Y(_03_));
  sky130_fd_sc_hd__a21oi_1 _24_ (.A1(count[0]), .A2(count[1]), .B1(count[2]), .Y(_16_));
  sky130_fd_sc_hd__nor2_1 _25_ (.A(_08_), .B(_16_), .Y(_02_));
  sky130_fd_sc_hd__xor2_1 _26_ (.A(count[0]), .B(count[1]), .X(_01_));
  sky130_fd_sc_hd__a41oi_1 _27_ (.A1(count[6]), .A2(count[5]), .A3(count[4]), .A4(_09_), .B1(count[7]), .Y(_17_));
  sky130_fd_sc_hd__a311oi_1 _28_ (.A1(count[6]), .A2(count[7]), .A3(_10_), .B1(tc), .C1(_17_), .Y(_07_));
  sky130_fd_sc_hd__and4_1 _29_ (.A(count[0]), .B(count[3]), .C(count[2]), .D(count[1]), .X(_09_));
  sky130_fd_sc_hd__and3_1 _30_ (.A(count[5]), .B(count[4]), .C(_09_), .X(_10_));
  sky130_fd_sc_hd__and4_1 _31_ (.A(count[6]), .B(count[5]), .C(count[4]), .D(_09_), .X(_11_));
  sky130_fd_sc_hd__nor3b_1 _32_ (.A(count[5]), .B(count[4]), .C_N(count[6]), .Y(_12_));
  sky130_fd_sc_hd__and4b_1 _33_ (.A_N(count[3]), .B(count[7]), .C(_08_), .D(_12_), .X(tc));
  sky130_fd_sc_hd__a31oi_1 _34_ (.A1(count[5]), .A2(count[4]), .A3(_09_), .B1(count[6]), .Y(_13_));
  sky130_fd_sc_hd__nor3_1 _35_ (.A(_11_), .B(tc), .C(_13_), .Y(_06_));
  sky130_fd_sc_hd__a21oi_1 _36_ (.A1(count[4]), .A2(_09_), .B1(count[5]), .Y(_14_));
  sky130_fd_sc_hd__dfrtp_1 _37_ (.CLK(clk), .D(_00_), .Q(count[0]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _38_ (.CLK(clk), .D(_01_), .Q(count[1]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _39_ (.CLK(clk), .D(_02_), .Q(count[2]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _40_ (.CLK(clk), .D(_03_), .Q(count[3]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _41_ (.CLK(clk), .D(_04_), .Q(count[4]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _42_ (.CLK(clk), .D(_05_), .Q(count[5]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _43_ (.CLK(clk), .D(_06_), .Q(count[6]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _44_ (.CLK(clk), .D(_07_), .Q(count[7]), .RESET_B(rst_n));
endmodule

ConceptHow many rows fit in a core 54.4 µm tall?

401920118

ConceptWhy is every other row flipped?

So that the cells in a row can face their neighbours' pinsSo that the router can reach the pins from both sidesSo that clock buffers can be placed between the rowsSo that two neighbouring rows share one supply or ground rail

ConceptWhy does the power grid use met4 and met5 rather than met1 and met2?

The upper layers are thicker, with several times lower sheet resistanceThe lower layers have no preferred direction, so straps would not fitOnly the upper layers can be connected to the I/O pinsThe lower layers are reserved for the clock tree by the foundry

ConceptWhich statement about routing tracks is wrong?

Each layer has its own tracks, spaced at its pitchA wire may run on any layer in any direction at no costThe met2 tracks line up with the columns of sitesA sky130 row is exactly eight met1 tracks tall

Remember

A floorplan is rows of sites: unithd is 0.46 × 2.72 µm, and the core snaps to whole sites and rows.
Every other row is flipped (N, FS) so that neighbouring rows share one VPWR or VGND rail.
SKY130 routes on li1 and met1-met5, alternating horizontal and vertical; upper layers are thicker and less resistive, so power goes high.
Tracks are the lines a router may use, one set per layer at its pitch; they are the routing supply.