Delay and slew from the Liberty tables

Two numbers set every delay

A static timing tool does not simulate transistors. It looks the delay of each cell up in tables that the library vendor measured once, for every input of every cell. Two numbers index each table.

The first is the input transition, or slew: how long the input takes to change. This library measures it from 20 % to 80 % of the supply. The second is the load: the total capacitance the output drives, which is the input capacitance of every pin on the net plus the wire. The delay runs from the input crossing 50 % to the output crossing 50 %.

Each table is a grid of 7 by 7 points: rows are input slews, columns are loads. This is the non-linear delay model (NLDM). Every arc has four tables: the delay for a rising and a falling output, and the output slew for each. The output slew becomes the next cell's input slew, so slew travels down the path with the arrival time.

Startpoint: ff1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: ffa (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                    0.1000    0.0000    0.0000 ^ ff1/CLK (sky130_fd_sc_hd__dfxtp_1)
     1    0.0022    0.0249    0.3082    0.3082 v ff1/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 q1 (net)
                    0.0249    0.0000    0.3082 v da/A (sky130_fd_sc_hd__inv_1)
     1    0.0024    0.0300    0.0377    0.3460 ^ da/Y (sky130_fd_sc_hd__inv_1)
                                                 na (net)
                    0.0300    0.0000    0.3460 ^ ua/A (sky130_fd_sc_hd__inv_1)
     1    0.0017    0.0150    0.0253    0.3713 v ua/Y (sky130_fd_sc_hd__inv_1)
                                                 ya (net)
                    0.0150    0.0000    0.3713 v ffa/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.3713   data arrival time

                    0.1000    1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock network delay (ideal)
                              0.0000    1.0000   clock reconvergence pessimism
                                        1.0000 ^ ffa/CLK (sky130_fd_sc_hd__dfxtp_1)
                             -0.0845    0.9155   library setup time
                                        0.9155   data required time
-------------------------------------------------------------------------------------
                                        0.9155   data required time
                                       -0.3713   data arrival time
-------------------------------------------------------------------------------------
                                        0.5442   slack (MET)

Each cell has its own load axis. inv_1's columns end at 0.1813 pF, nand2_1's at 0.1666 pF, each cell's max_capacitance. Column 4 of one table is a different load from column 4 of another, so always read the index values.

Look a delay up by hand

Take the inverter in the two-flop path. The flop's output rises with a slew of 0.0388 ns and drives inv_1, whose falling output drives one nand2_1 input. A falling input pin of nand2_1 presents 0.002254 pF. Neither number is on the grid, so the tool interpolates between the four surrounding points.

1. Find the fractions

   The slew sits 0.5235 of the way from row 2 to row 3. The load sits 0.4120 of the way from column 2 to column 3.

2. Interpolate along the load

   In row 2: 0.0219910 + 0.4120 × (0.0299354 − 0.0219910) = 0.025264 ns. In row 3 the same step gives 0.034954 ns.

3. Interpolate along the slew

   0.025264 + 0.5235 × (0.034954 − 0.025264) = 0.030337 ns. Rounded to four places, 0.0303 ns.

4. The output slew

   The fall_transition table, read the same way, gives 0.018760 ns. That becomes nand2_1's input slew.

OpenSTA reports 0.0303 ns for this arc and an output slew of 0.0188 ns, in the Try it below. With no wires, the tool's delay is exactly this bilinear interpolation. With extracted wires, OpenSTA first reduces the wire to an effective capacitance, a later lesson's subject.

Delay grows with load, and the table ends

Sweep the load and the delay rises with it. Past about 10 fF each extra femtofarad adds a nearly fixed 3.3 ps: a straight line, which the logarithmic axis bends into a curve. A slower input lifts the curve at almost every load. The plot is one OpenSTA run of 52 inverters, each with its own input slew and load.

Past the last column the number is a guess. Extending the table by hand gives 0.8558 ns, the same as the tool, with an output slew of 1.1124 ns. That is why every output pin carries a max_capacitance and the library a default_max_transition of 1.5 ns. Beyond them the tool still prints a number, and a design-rule check reports the violation.

Try it shows that check too. With a 0.25 pF load, its Output lists u1/Y under the design rules: over its max_capacitance of 0.1813 pF, and over its max slew as well. L4 repairs such violations in the flow.

A flop drives with its own output stage

A flip-flop has tables too: from CLK to Q. Its delay grows with the clock slew, but its output slew hardly moves. A slow clock edge only delays the moment Q starts to switch; how fast Q then switches depends on what Q drives. Here the clock slew runs from 0.01 to 1.5 ns. Clock-to-Q rises from 0.2724 to 0.5105 ns, while the Q slew stays near 0.0226 ns.

So a slow clock edge costs time at every flop, which is one reason the clock tree in L5 keeps its slews short.

Try it

The netlist is one inverter between an input port and an output port. The SDC sets the input slew and the output load, and asks for the falling output. Run it and find the u1/Y line: the Slew and Delay columns are the two lookups worked above.

Now change the load to 0.00952062, a column of the table, and predict the delay before you run. Then try 0.25: the report still prints a number, 0.8558 ns, although the load is past max_capacitance.

module dcalc (a, y);
  input a;
  output y;
  sky130_fd_sc_hd__inv_1 u1 (.A(a), .Y(y));
endmodule

Check yourself

set_input_transition 0.0531329 [get_ports a]
set_load 0.00133517 [get_ports y]
set_max_delay 1.0 -from [get_ports a] -fall_to [get_ports y]

module dcalc (a, y);
  input a;
  output y;
  sky130_fd_sc_hd__inv_1 u1 (.A(a), .Y(y));
endmodule