The timing graph: arrival times and slew

Follow how a timing tool walks the netlist once, carrying arrival times and slews pin by pin, and why a path can inherit a slew from a gate input it never passes through.

Lesson: L2.3
Time: 25 min
Runs on: OpenROAD
Check: 5 questions

A report through the A input of a NAND showed an output slew of 0.0781 ns. A's own arc gives about 0.0344 ns at that load. The slow edge came from the other input, B, driven by an inv_1 that also feeds 32 flops.

Timing pathThe path through the NAND's A inputFlop ffa launches through c1 and c2 (inv_1) into A of g (nand2_1); o (inv_1) drives flop ffc. B of g comes from w (inv_1), which drives 32 flop D pins.

ffa → ffcsetup check, latest arrival5 cells

Clock latency
Cell delay
Setup time

A arrives fast
A changes at 0.3735 ns with a 0.0172 ns slew.
A slow output edge
The report gives g's output a 0.0781 ns slew. A's own table gives 0.0344 ns.
The next cell pays
o takes 0.0368 ns at that slew. At A's own slew its table gives 0.0266 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 1.0000 ns, latency 0.0000 ns, library setup time −0.0885 ns.

Arrival 0.4497 ns, required 0.9115 ns, slack 0.4618 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`ffa/CLK` → `ffa/Q`	dfxtp_1	fall	0.3082	0.3082	0.0249
	`ffa/Q` → `c1/A`	wire qa	fall	0.0000	0.3082	0.0249
2	`c1/A` → `c1/Y`	inv_1	rise	0.0377	0.3460	0.0300
	`c1/Y` → `c2/A`	wire na1	rise	0.0000	0.3460	0.0300
3	`c2/A` → `c2/Y`	inv_1	fall	0.0275	0.3735	0.0172
	`c2/Y` → `g/A`	wire na2	fall	0.0000	0.3735	0.0172
4	`g/A` → `g/Y`	nand2_1	rise	0.0395	0.4130	0.0781
	`g/Y` → `o/A`	wire ny	rise	0.0000	0.4130	0.0781
5	`o/A` → `o/Y`	inv_1	fall	0.0368	0.4497	0.0240
	`o/Y` → `ffc/D`	wire no	fall	0.0000	0.4497	0.0240

The report

Startpoint: ffa (rising edge-triggered flip-flop clocked by clk)
Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                    0.1000    0.0000    0.0000 ^ ffa/CLK (sky130_fd_sc_hd__dfxtp_1)
     1    0.0022    0.0249    0.3082    0.3082 v ffa/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 qa (net)
                    0.0249    0.0000    0.3082 v c1/A (sky130_fd_sc_hd__inv_1)
     1    0.0024    0.0300    0.0377    0.3460 ^ c1/Y (sky130_fd_sc_hd__inv_1)
                                                 na1 (net)
                    0.0300    0.0000    0.3460 ^ c2/A (sky130_fd_sc_hd__inv_1)
     1    0.0023    0.0172    0.0275    0.3735 v c2/Y (sky130_fd_sc_hd__inv_1)
                                                 na2 (net)
                    0.0172    0.0000    0.3735 v g/A (sky130_fd_sc_hd__nand2_1)
     1    0.0024    0.0781    0.0395    0.4130 ^ g/Y (sky130_fd_sc_hd__nand2_1)
                                                 ny (net)
                    0.0781    0.0000    0.4130 ^ o/A (sky130_fd_sc_hd__inv_1)
     1    0.0017    0.0240    0.0368    0.4497 v o/Y (sky130_fd_sc_hd__inv_1)
                                                 no (net)
                    0.0240    0.0000    0.4497 v ffc/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.4497   data arrival time

                    0.1000    1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock network delay (ideal)
                              0.0000    1.0000   clock reconvergence pessimism
                                        1.0000 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
                             -0.0885    0.9115   library setup time
                                        0.9115   data required time
-------------------------------------------------------------------------------------
                                        0.9115   data required time
                                       -0.4497   data arrival time
-------------------------------------------------------------------------------------
                                        0.4618   slack (MET)

OpenSTA 3.1.0 on the sky130 tt library, ideal 1 ns clock, no wires; paths through g/A only.

The tool keeps one slew per pin and edge, and uses it for every path through that pin.

Pins are nodes, arcs are edges

A timing tool turns the netlist into a timing graph. Every pin is a node. Every cell arc (L2.1) is an edge, and so is every net, from its driver to each load.

Paths start at startpoints: input ports, and the clock pins of flops, where the clock-to-Q arc leaves. They end at endpoints: flop data pins, where setup and hold are checked, and output ports. A clock pin is never an endpoint of a data path.

The two-flop path as a timing graphNodes are pins; arrows are nets and cell arcs, in the direction a signal travels. Times are setup (latest) arrivals from the run below.

Start and end
Three startpoints (a, b and ff1's clock pin) and two flop endpoints. ff2's clock pin also starts a path, to the output port y, which is not drawn.
One pass forward
The tool visits each pin once, in order: ff1/Q at 0.3082 ns, u1/Y at 0.3459 ns.
Two arrivals meet
u2/Y can be reached through A or through B. The latest falling arrival comes through A, at 0.3789 ns. The earliest rising one comes from b, at 0.2350 ns.
The endpoint
ff2/D inherits both: 0.3789 ns for setup, 0.2350 ns for hold.

Read the diagram as text

a (input port): startpoint
ff1/CLK: startpoint
b (input port): startpoint
ff1/D: endpoint
ff1/Q: 0.3082 ns
u1/Y: 0.3459 ns
u2/Y: 0.3789 ns
ff2/D: endpoint

a (input port) → ff1/D: net
ff1/CLK → ff1/Q: clock to Q
ff1/Q → u1/Y: net, inv_1
u1/Y → u2/Y: net, nand2_1 A
b (input port) → u2/Y: net, nand2_1 B
u2/Y → ff2/D: net

path2 with a 0.2 ns input delay on a and b and a 0.2 ns output delay on y.

Path kind	Starts at	Ends at	In this design
input to register	input port	flop data pin	a to ff1/D, b to ff2/D
register to register	flop clock pin	flop data pin	ff1/CLK to ff2/D
register to output	flop clock pin	output port	ff2/CLK to y
input to output	input port	output port	none: no port drives logic straight to a port

The four kinds of path. The input and output delays in the SDC give the port paths their launch and capture times.

Latest for setup, earliest for hold

At each pin the tool computes an arrival time: when the signal there changes, counted from the launching clock edge. It keeps one for a rising and one for a falling signal, because every inverting arc swaps the two (L2.1). Where several edges meet, setup analysis keeps the latest arrival and hold analysis the earliest. One forward pass fills every pin.

The tool never lists paths while it does this. A design with many reconverging gates has far more paths than pins, so listing them would be hopeless. A path is recovered afterwards, by tracing back from an endpoint along the edges that set each arrival.

Timing pathSetup at ff2/D: the latest arrival, through AThe trace-back from ff2/D for the max (setup) check.

ff1 → ff2setup check, latest arrival3 cells

Clock latency
Cell delay
Setup time

The later edge
The latest falling edge at u2/Y comes through A, at 0.3789 ns.
Setup slack
0.5329 ns at a 1 ns period.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 1.0000 ns, latency 0.0000 ns, library setup time −0.0882 ns.

Arrival 0.3789 ns, required 0.9118 ns, slack 0.5329 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`ff1/CLK` → `ff1/Q`	dfxtp_1	fall	0.3082	0.3082	0.0249
	`ff1/Q` → `u1/A`	wire q1	fall	0.0000	0.3082	0.0249
2	`u1/A` → `u1/Y`	inv_1	rise	0.0376	0.3459	0.0299
	`u1/Y` → `u2/A`	wire n1	rise	0.0000	0.3459	0.0299
3	`u2/A` → `u2/Y`	nand2_1	fall	0.0330	0.3789	0.0233
	`u2/Y` → `ff2/D`	wire n2	fall	0.0000	0.3789	0.0233

The report

Startpoint: ff1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: ff2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                    0.1000    0.0000    0.0000 ^ ff1/CLK (sky130_fd_sc_hd__dfxtp_1)
     1    0.0022    0.0249    0.3082    0.3082 v ff1/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 q1 (net)
                    0.0249    0.0000    0.3082 v u1/A (sky130_fd_sc_hd__inv_1)
     1    0.0024    0.0299    0.0376    0.3459 ^ u1/Y (sky130_fd_sc_hd__inv_1)
                                                 n1 (net)
                    0.0299    0.0000    0.3459 ^ u2/A (sky130_fd_sc_hd__nand2_1)
     1    0.0017    0.0233    0.0330    0.3789 v u2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0233    0.0000    0.3789 v ff2/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.3789   data arrival time

                    0.1000    1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock network delay (ideal)
                              0.0000    1.0000   clock reconvergence pessimism
                                        1.0000 ^ ff2/CLK (sky130_fd_sc_hd__dfxtp_1)
                             -0.0882    0.9118   library setup time
                                        0.9118   data required time
-------------------------------------------------------------------------------------
                                        0.9118   data required time
                                       -0.3789   data arrival time
-------------------------------------------------------------------------------------
                                        0.5329   slack (MET)

OpenSTA 3.1.0, ideal clock, path2 with input and output delays.

Timing pathHold at ff2/D: the earliest arrival, from bThe trace-back from the same endpoint for the min (hold) check starts at another startpoint.

b → ff2hold check, earliest arrival1 cell

Clock latency
Cell delay
Input delay
Hold time

Input delay
b changes 0.2 ns after the clock edge, as the SDC says.
The earlier edge
Through B, u2/Y changes at 0.2350 ns, before anything from ff1 arrives.
Hold slack
0.2555 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 0.0000 ns, latency 0.0000 ns, library hold time −0.0205 ns.

Arrival 0.2350 ns, required −0.0205 ns, slack 0.2555 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
	`b` → `u2/B`	wire b	fall	0.0000	0.2000	0.0000
1	`u2/B` → `u2/Y`	nand2_1	rise	0.0350	0.2350	0.0281
	`u2/Y` → `ff2/D`	wire n2	rise	0.0000	0.2350	0.0281

The report

Startpoint: b (input port clocked by clk)
Endpoint: ff2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                              0.2000    0.2000 v input external delay
     1    0.0022    0.0000    0.0000    0.2000 v b (in)
                                                 b (net)
                    0.0000    0.0000    0.2000 v u2/B (sky130_fd_sc_hd__nand2_1)
     1    0.0017    0.0281    0.0350    0.2350 ^ u2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0281    0.0000    0.2350 ^ ff2/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.2350   data arrival time

                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                              0.0000    0.0000   clock reconvergence pessimism
                                        0.0000 ^ ff2/CLK (sky130_fd_sc_hd__dfxtp_1)
                             -0.0205   -0.0205   library hold time
                                       -0.0205   data required time
-------------------------------------------------------------------------------------
                                       -0.0205   data required time
                                       -0.2350   data arrival time
-------------------------------------------------------------------------------------
                                        0.2555   slack (MET)

The same run, min path.

So one endpoint can have its setup path and its hold path start in different places.

Slew travels, and merges at a pin

Slew moves with the arrival. Each arc's output slew comes from its table at the input slew and the load (L2.2). When two arcs reach one pin, the tool keeps the worst slew for each edge, separately for setup and for hold. For setup that is the slowest edge, because it delays every later cell. Every path through that pin then uses it.

That is the hook. B's driver, inv_1 with 32 flop loads, changes slowly, so B's arc gives g the slowest output edge. The path through A inherits it, and o after g gets slower. Nothing on the A path changed.

Measured sweepArrival of the A path against the fanout of B's driverSixteen copies of the netlist in one OpenSTA run; only paths through each NAND's A input are reported.

B driven by inv_1
B driven by inv_4

Flop loads on B's driver 1B driven by inv_1 = 441.5 ps · B driven by inv_4 = 441.5 ps
One load: 0.4415 ns with inv_1, 0.4415 ns with inv_4.
Flop loads on B's driver 32B driven by inv_1 = 449.7 ps · B driven by inv_4 = 442.4 ps
32 loads: 0.4497 against 0.4424 ns. Upsizing a gate off the path saves 7.3 ps on it.
Flop loads on B's driver 64B driven by inv_1 = 456.2 ps · B driven by inv_4 = 445.4 ps
64 loads: 0.4562 ns with inv_1. The A path never touches B's driver.

Read the plot as a table

Flop loads on B's driver	B driven by inv_1	B driven by inv_4
1	441.5 ps	441.5 ps
10	443.4 ps	441.5 ps
20	446.6 ps	441.8 ps
30	449.2 ps	442.3 ps
32	449.7 ps	442.4 ps
40	451.4 ps	443.1 ps
50	453.5 ps	444.1 ps
60	455.4 ps	445 ps
64	456.2 ps	445.4 ps

OpenSTA 3.1.0, sky130_fd_sc_hd tt library, ideal 1 ns clock, no wires.

You can check the merge by hand with the tables. o's cell_fall table at the merged slew, 0.0781 ns, and a flop D load gives 0.0368 ns, the report's number. At A's own slew, 0.0344 ns, the same table gives 0.0266 ns. The difference is the price of the merge on this one cell, and it repeats at every later cell whose input slew grew.

Keeping one slew per pin is graph-based analysis. It is safe, because no path is timed with a faster edge than it could see. It is pessimistic, because the A path is charged for B's slow edge even when B is steady. Path-based analysis re-times one path with only the slews along it; the OpenSTA build here has no such mode.

Asked in interviews

How does STA find the worst path without listing every path?
It propagates arrival times forward through the timing graph once, keeping the latest (setup) or earliest (hold) arrival at each pin. The worst path is traced back from the worst endpoint.
What are the four kinds of timing path?
Input to register, register to register, register to output and input to output. Startpoints are input ports and flop clock pins; endpoints are flop data pins and output ports.
What is graph-based versus path-based analysis?
Graph-based analysis keeps one worst slew and arrival per pin for all paths: fast and safe, but pessimistic. Path-based analysis re-times a chosen path with its own slews to remove that pessimism.
Why can a path improve when you upsize a gate that is not on it?
The gate drives another input of a cell on the path. Its sharper edge lowers the worst slew kept at that cell's output, so the cells after it on the path get faster.

Try it

This is the hook's netlist: 32 sink flops on B's driver w. The request reports only paths through g/A. Run it and find the g/Y line: slew 0.0781 ns, and the path arrives at 0.4497 ns.

Now change w from sky130_fd_sc_hd__inv_1 to sky130_fd_sc_hd__inv_4 and run again. The A path arrives at 0.4424 ns. Then try removing sink flops instead, or raise the slew on en in the SDC.

STAOpenSTA in OpenROAD 26Q2 · sky130hd tt_025C_1v80 Liberty · simulator service

Edit the constraints or the netlist, then run

Expected: path 1 arrival 0.4497 ns path 1 arc 7 slew 0.0781 ns

Check yourself

Predict the outputThe two-flop path with b's input delay lowered from 0.2 to 0.1 ns. What worst hold slack (WHS) does OpenSTA report, in ns?

create_clock -name clk -period 1.0 [get_ports clk]
set_clock_transition 0.1 [all_clocks]
set_input_delay 0.2 -clock clk [get_ports a]
set_input_delay 0.1 -clock clk [get_ports b]
set_output_delay 0.2 -clock clk [get_ports y]

ConceptOne of these path descriptions cannot be a timing path in path2. Which one?

From ff2/CLK to output port y, a register-to-output pathFrom ff1/CLK to ff2/D, a register-to-register pathFrom input port b to ff2/D, an input-to-register pathFrom ff1/D to ff2/CLK, ending at the capture clock pin

ConceptWhy does a timing tool not enumerate every path to find the worst one?

Paths grow far faster than pins; one forward pass covers allIt times only the paths that the SDC lists by nameIt samples random paths and bounds the rest statisticallyEach endpoint has one path, so there is nothing to list

ConceptIn the plot, upsizing B's driver to inv_4 makes the A path 7.3 ps faster at 32 loads. Why?

The A path now passes through the faster inv_4 instead of the inv_1B's sharper edge lowers the worst slew kept at g/Y, which speeds up oinv_4 loads the input port en less, so A arrives earlier at the NANDThe capture flop's setup time shrinks because its clock edge is sharper

ConceptTwo arcs reach one pin with output slews of 0.03 and 0.12 ns. Which slews does the tool keep there?

The average, 0.075 ns, for both checks0.03 ns for setup and 0.12 ns for hold0.12 ns for setup and 0.03 ns for hold0.12 ns for both setup and hold

Remember

A timing graph has pins as nodes and cell arcs and nets as edges; paths start at input ports and flop clock pins and end at flop data pins and output ports.
One forward pass computes rise and fall arrivals at every pin, latest for setup and earliest for hold; paths are traced back afterwards.
Slew travels with the arrival, and where arcs meet the tool keeps the worst slew per edge for every path through the pin.
Graph-based slew merging is safe and pessimistic: a gate off the path can slow it, and upsizing that gate can speed it up.