Corners, derates, OCV and CPPR

Check setup and hold at the corners where each is worst, model on-chip variation with derates, and read the pessimism credit that CPPR gives back.

Lesson: L2.9
Time: 30 min
Runs on: OpenROAD
Check: 5 questions

A small block met setup at the typical corner with 0.5262 ns to spare. Read with the slow Liberty at −40 °C and 1.60 V, the same path failed by 0.1328 ns. A chip has to work over a range of process, voltage and temperature, and the typical file shows only its middle.

Timing pathThe same setup path at the slow cornerFlop ffl launches, ffc captures; both clocks come from one clkbuf_4 and their own clkbuf_1. Liberty sky130_fd_sc_hd__ss_n40C_1v60.

ffl → ffcsetup check, latest arrival2 cells

Clock latency
Cell delay
Setup time

A slower clock
The clock reaches ffl after 0.3654 ns, against 0.2071 ns at typical.
A slower path
Clock-to-Q and two gates: arrival 1.1566 ns, against 0.5768 ns.
Violated
The flop's setup time grows too, to 0.3416 ns. Slack -0.1328 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.3654 ns. Capture: clk rise edge at 1.0000 ns, latency 0.3654 ns, library setup time −0.3416 ns.

Arrival 1.1566 ns, required 1.0238 ns, slack −0.1328 ns (violated).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`ffl/CLK` → `ffl/Q`	dfxtp_1	rise	0.6990	1.0644	0.1122
	`ffl/Q` → `u2/B`	wire q1	rise	0.0000	1.0644	0.1122
2	`u2/B` → `u2/Y`	nand2_1	fall	0.0921	1.1566	0.0374
	`u2/Y` → `ffc/D`	wire n2	fall	0.0000	1.1566	0.0374

The report

Startpoint: ffl (rising edge-triggered flip-flop clocked by clk)
Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0021    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0040    0.0573    0.2271    0.2271 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0573    0.0000    0.2271 ^ bl/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0016    0.0684    0.1383    0.3654 ^ bl/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl (net)
                    0.0684    0.0000    0.3654 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1)
     2    0.0044    0.1122    0.6990    1.0644 ^ ffl/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 q1 (net)
                    0.1122    0.0000    1.0644 ^ u2/B (sky130_fd_sc_hd__nand2_1)
     1    0.0015    0.0374    0.0921    1.1566 v u2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0374    0.0000    1.1566 v ffc/D (sky130_fd_sc_hd__dfxtp_1)
                                        1.1566   data arrival time

                              1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock source latency
     1    0.0021    0.1000    0.0000    1.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0040    0.0573    0.2271    1.2271 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0573    0.0000    1.2271 ^ bc/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0016    0.0684    0.1383    1.3654 ^ bc/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cc (net)
                    0.0684    0.0000    1.3654 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    1.3654   clock reconvergence pessimism
                             -0.3416    1.0238   library setup time
                                        1.0238   data required time
-------------------------------------------------------------------------------------
                                        1.0238   data required time
                                       -1.1566   data arrival time
-------------------------------------------------------------------------------------
                                       -0.1328   slack (VIOLATED)

OpenSTA 3.1.0, propagated 1 ns clock with a 0.1 ns slew at the port, no wires.

Setup and hold fail at opposite ends of that range, so sign-off checks each where it is worst.

Corners: one Liberty file per condition

A corner is one combination of process, voltage and temperature, with its own Liberty file. Process is slow (ss), typical (tt) or fast (ff) transistors. The file name says the rest: ss_n40C_1v60 is slow transistors at −40 °C and 1.60 V. The SKY130 release ships sixteen timing corners for this library; these lessons use four.

Corner	Setup slack	Hold slack
tt_025C_1v80 (typical)	0.5262 ns	0.3730 ns
ss_n40C_1v60 (slow, cold)	-0.1328 ns	0.7501 ns
ff_n40C_1v95 (fast, cold)	0.6973 ns	0.2397 ns

The same netlist and SDC read with three Liberty files. OpenSTA 3.1.0, no derates.

Setup is worst where cells are slowest, hold where they are fastest. Here hold slack drops from 0.3730 ns at typical to 0.2397 ns at the fast corner, while setup gains. So sign-off checks setup at the slow corners and hold at the fast ones, and usually both everywhere.

Which slow corner is slower is not obvious. At the same 1.60 V, the hot slow corner ss_100C_1v60 gives setup slack -0.0059 ns, and the cold one -0.1328 ns. On slow transistors at 1.60 V these cells are slower when cold. The cold raises the threshold voltage, and here that outweighs the faster carriers. This is called temperature inversion, and it is why both temperatures are checked.

The paths behind the table

Timing pathSetup at tt_025C_1v80

ffl → ffcsetup check, latest arrival3 cells

Clock latency
Cell delay
Setup time

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.2071 ns. Capture: clk rise edge at 1.0000 ns, latency 0.2071 ns, library setup time −0.1040 ns.

Arrival 0.5768 ns, required 1.1030 ns, slack 0.5262 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`ffl/CLK` → `ffl/Q`	dfxtp_1	fall	0.2947	0.5017	0.0345
	`ffl/Q` → `u1/A`	wire q1	fall	0.0000	0.5017	0.0345
2	`u1/A` → `u1/Y`	inv_1	rise	0.0417	0.5435	0.0308
	`u1/Y` → `u2/A`	wire n1	rise	0.0000	0.5435	0.0308
3	`u2/A` → `u2/Y`	nand2_1	fall	0.0333	0.5768	0.0251
	`u2/Y` → `ffc/D`	wire n2	fall	0.0000	0.5768	0.0251

The report

Startpoint: ffl (rising edge-triggered flip-flop clocked by clk)
Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0044    0.0334    0.1381    0.1381 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0334    0.0000    0.1381 ^ bl/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0690    0.2071 ^ bl/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl (net)
                    0.0353    0.0000    0.2071 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1)
     2    0.0044    0.0345    0.2947    0.5017 v ffl/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 q1 (net)
                    0.0345    0.0000    0.5017 v u1/A (sky130_fd_sc_hd__inv_1)
     1    0.0024    0.0308    0.0417    0.5435 ^ u1/Y (sky130_fd_sc_hd__inv_1)
                                                 n1 (net)
                    0.0308    0.0000    0.5435 ^ u2/A (sky130_fd_sc_hd__nand2_1)
     1    0.0017    0.0251    0.0333    0.5768 v u2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0251    0.0000    0.5768 v ffc/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.5768   data arrival time

                              1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock source latency
     1    0.0022    0.1000    0.0000    1.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0044    0.0334    0.1381    1.1381 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0334    0.0000    1.1381 ^ bc/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0690    1.2071 ^ bc/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cc (net)
                    0.0353    0.0000    1.2071 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    1.2071   clock reconvergence pessimism
                             -0.1040    1.1030   library setup time
                                        1.1030   data required time
-------------------------------------------------------------------------------------
                                        1.1030   data required time
                                       -0.5768   data arrival time
-------------------------------------------------------------------------------------
                                        0.5262   slack (MET)

The typical corner, setup: the reference for the other rows.

Timing pathHold at tt_025C_1v80

ffl → ffchold check, earliest arrival2 cells

Clock latency
Cell delay
Hold time

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.2071 ns. Capture: clk rise edge at 0.0000 ns, latency 0.2071 ns, library hold time −0.0290 ns.

Arrival 0.5511 ns, required 0.1781 ns, slack 0.3730 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`ffl/CLK` → `ffl/Q`	dfxtp_1	fall	0.2947	0.5017	0.0345
	`ffl/Q` → `u2/B`	wire q1	fall	0.0000	0.5017	0.0345
2	`u2/B` → `u2/Y`	nand2_1	rise	0.0493	0.5511	0.0281
	`u2/Y` → `ffc/D`	wire n2	rise	0.0000	0.5511	0.0281

The report

Startpoint: ffl (rising edge-triggered flip-flop clocked by clk)
Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0044    0.0334    0.1381    0.1381 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0334    0.0000    0.1381 ^ bl/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0690    0.2071 ^ bl/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl (net)
                    0.0353    0.0000    0.2071 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1)
     2    0.0044    0.0345    0.2947    0.5017 v ffl/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 q1 (net)
                    0.0345    0.0000    0.5017 v u2/B (sky130_fd_sc_hd__nand2_1)
     1    0.0017    0.0281    0.0493    0.5511 ^ u2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0281    0.0000    0.5511 ^ ffc/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.5511   data arrival time

                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0044    0.0334    0.1381    0.1381 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0334    0.0000    0.1381 ^ bc/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0690    0.2071 ^ bc/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cc (net)
                    0.0353    0.0000    0.2071 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    0.2071   clock reconvergence pessimism
                             -0.0290    0.1781   library hold time
                                        0.1781   data required time
-------------------------------------------------------------------------------------
                                        0.1781   data required time
                                       -0.5511   data arrival time
-------------------------------------------------------------------------------------
                                        0.3730   slack (MET)

The typical corner, hold: the same path checked at the launch edge.

Timing pathHold at ss_n40C_1v60

ffl → ffchold check, earliest arrival2 cells

Clock latency
Cell delay
Hold time

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.3654 ns. Capture: clk rise edge at 0.0000 ns, latency 0.3654 ns, library hold time −0.0554 ns.

Arrival 1.0601 ns, required 0.3100 ns, slack 0.7501 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`ffl/CLK` → `ffl/Q`	dfxtp_1	fall	0.5972	0.9626	0.0509
	`ffl/Q` → `u2/B`	wire q1	fall	0.0000	0.9626	0.0509
2	`u2/B` → `u2/Y`	nand2_1	rise	0.0975	1.0601	0.0552
	`u2/Y` → `ffc/D`	wire n2	rise	0.0000	1.0601	0.0552

The report

Startpoint: ffl (rising edge-triggered flip-flop clocked by clk)
Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0021    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0040    0.0573    0.2271    0.2271 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0573    0.0000    0.2271 ^ bl/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0016    0.0684    0.1383    0.3654 ^ bl/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl (net)
                    0.0684    0.0000    0.3654 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1)
     2    0.0041    0.0509    0.5972    0.9626 v ffl/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 q1 (net)
                    0.0509    0.0000    0.9626 v u2/B (sky130_fd_sc_hd__nand2_1)
     1    0.0015    0.0552    0.0975    1.0601 ^ u2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0552    0.0000    1.0601 ^ ffc/D (sky130_fd_sc_hd__dfxtp_1)
                                        1.0601   data arrival time

                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0021    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0040    0.0573    0.2271    0.2271 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0573    0.0000    0.2271 ^ bc/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0016    0.0684    0.1383    0.3654 ^ bc/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cc (net)
                    0.0684    0.0000    0.3654 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    0.3654   clock reconvergence pessimism
                             -0.0554    0.3100   library hold time
                                        0.3100   data required time
-------------------------------------------------------------------------------------
                                        0.3100   data required time
                                       -1.0601   data arrival time
-------------------------------------------------------------------------------------
                                        0.7501   slack (MET)

The slow, cold corner, hold: slow cells give hold plenty of room.

Timing pathSetup at ff_n40C_1v95

ffl → ffcsetup check, latest arrival3 cells

Clock latency
Cell delay
Setup time

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.1420 ns. Capture: clk rise edge at 1.0000 ns, latency 0.1420 ns, library setup time −0.0655 ns.

Arrival 0.3792 ns, required 1.0765 ns, slack 0.6973 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`ffl/CLK` → `ffl/Q`	dfxtp_1	fall	0.1879	0.3300	0.0247
	`ffl/Q` → `u1/A`	wire q1	fall	0.0000	0.3300	0.0247
2	`u1/A` → `u1/Y`	inv_1	rise	0.0293	0.3593	0.0227
	`u1/Y` → `u2/A`	wire n1	rise	0.0000	0.3593	0.0227
3	`u2/A` → `u2/Y`	nand2_1	fall	0.0199	0.3792	0.0179
	`u2/Y` → `ffc/D`	wire n2	fall	0.0000	0.3792	0.0179

The report

Startpoint: ffl (rising edge-triggered flip-flop clocked by clk)
Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0023    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0045    0.0251    0.0966    0.0966 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0251    0.0000    0.0966 ^ bl/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0260    0.0454    0.1420 ^ bl/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl (net)
                    0.0260    0.0000    0.1420 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1)
     2    0.0044    0.0247    0.1879    0.3300 v ffl/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 q1 (net)
                    0.0247    0.0000    0.3300 v u1/A (sky130_fd_sc_hd__inv_1)
     1    0.0024    0.0227    0.0293    0.3593 ^ u1/Y (sky130_fd_sc_hd__inv_1)
                                                 n1 (net)
                    0.0227    0.0000    0.3593 ^ u2/A (sky130_fd_sc_hd__nand2_1)
     1    0.0018    0.0179    0.0199    0.3792 v u2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0179    0.0000    0.3792 v ffc/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.3792   data arrival time

                              1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock source latency
     1    0.0023    0.1000    0.0000    1.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0045    0.0251    0.0966    1.0966 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0251    0.0000    1.0966 ^ bc/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0260    0.0454    1.1420 ^ bc/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cc (net)
                    0.0260    0.0000    1.1420 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    1.1420   clock reconvergence pessimism
                             -0.0655    1.0765   library setup time
                                        1.0765   data required time
-------------------------------------------------------------------------------------
                                        1.0765   data required time
                                       -0.3792   data arrival time
-------------------------------------------------------------------------------------
                                        0.6973   slack (MET)

The fast corner, setup: fast cells give setup its largest slack.

Timing pathHold at ff_n40C_1v95

ffl → ffchold check, earliest arrival2 cells

Clock latency
Cell delay
Hold time

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.1420 ns. Capture: clk rise edge at 0.0000 ns, latency 0.1420 ns, library hold time −0.0167 ns.

Arrival 0.3650 ns, required 0.1253 ns, slack 0.2397 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`ffl/CLK` → `ffl/Q`	dfxtp_1	fall	0.1879	0.3300	0.0247
	`ffl/Q` → `u2/B`	wire q1	fall	0.0000	0.3300	0.0247
2	`u2/B` → `u2/Y`	nand2_1	rise	0.0351	0.3650	0.0210
	`u2/Y` → `ffc/D`	wire n2	rise	0.0000	0.3650	0.0210

The report

Startpoint: ffl (rising edge-triggered flip-flop clocked by clk)
Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0023    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0045    0.0251    0.0966    0.0966 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0251    0.0000    0.0966 ^ bl/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0260    0.0454    0.1420 ^ bl/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl (net)
                    0.0260    0.0000    0.1420 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1)
     2    0.0044    0.0247    0.1879    0.3300 v ffl/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 q1 (net)
                    0.0247    0.0000    0.3300 v u2/B (sky130_fd_sc_hd__nand2_1)
     1    0.0017    0.0210    0.0351    0.3650 ^ u2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0210    0.0000    0.3650 ^ ffc/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.3650   data arrival time

                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0023    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0045    0.0251    0.0966    0.0966 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0251    0.0000    0.0966 ^ bc/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0260    0.0454    0.1420 ^ bc/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cc (net)
                    0.0260    0.0000    0.1420 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    0.1420   clock reconvergence pessimism
                             -0.0167    0.1253   library hold time
                                        0.1253   data required time
-------------------------------------------------------------------------------------
                                        0.1253   data required time
                                       -0.3650   data arrival time
-------------------------------------------------------------------------------------
                                        0.2397   slack (MET)

The fast corner, hold: the smallest hold slack of the three corners.

Timing pathSetup at ss_100C_1v60

ffl → ffcsetup check, latest arrival2 cells

Clock latency
Cell delay
Setup time

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.3593 ns. Capture: clk rise edge at 1.0000 ns, latency 0.3593 ns, library setup time −0.2659 ns.

Arrival 1.0993 ns, required 1.0934 ns, slack −0.0059 ns (violated).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`ffl/CLK` → `ffl/Q`	dfxtp_1	rise	0.6394	0.9987	0.0971
	`ffl/Q` → `u2/B`	wire q1	rise	0.0000	0.9987	0.0971
2	`u2/B` → `u2/Y`	nand2_1	fall	0.1006	1.0993	0.0535
	`u2/Y` → `ffc/D`	wire n2	fall	0.0000	1.0993	0.0535

The report

Startpoint: ffl (rising edge-triggered flip-flop clocked by clk)
Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0042    0.0568    0.2295    0.2295 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0568    0.0000    0.2295 ^ bl/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0017    0.0560    0.1298    0.3593 ^ bl/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl (net)
                    0.0560    0.0000    0.3593 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1)
     2    0.0047    0.0971    0.6394    0.9987 ^ ffl/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 q1 (net)
                    0.0971    0.0000    0.9987 ^ u2/B (sky130_fd_sc_hd__nand2_1)
     1    0.0016    0.0535    0.1006    1.0993 v u2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0535    0.0000    1.0993 v ffc/D (sky130_fd_sc_hd__dfxtp_1)
                                        1.0993   data arrival time

                              1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock source latency
     1    0.0022    0.1000    0.0000    1.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0042    0.0568    0.2295    1.2295 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0568    0.0000    1.2295 ^ bc/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0017    0.0560    0.1298    1.3593 ^ bc/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cc (net)
                    0.0560    0.0000    1.3593 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    1.3593   clock reconvergence pessimism
                             -0.2659    1.0934   library setup time
                                        1.0934   data required time
-------------------------------------------------------------------------------------
                                        1.0934   data required time
                                       -1.0993   data arrival time
-------------------------------------------------------------------------------------
                                       -0.0059   slack (VIOLATED)

The slow, hot corner at the same voltage, setup: slower than typical, faster than cold.

OpenSTA can read several corners in one run with define_corners and read_liberty -corner. The lab here reads one Liberty file per run.

On-chip variation and derates

Inside one die at one corner, two copies of the same cell still differ: dopant counts, line widths and local voltage vary. On-chip variation (OCV) is modelled with derates, factors on every delay. set_timing_derate -late 1.05 makes delays 5 % longer where a longer delay hurts, and -early 0.95 makes them 5 % shorter where a shorter one hurts.

ctree: which delays are late for setupArrows are the clock and data. For setup the launch side is late and the capture side early; hold swaps them.

Launch side late
For setup, the launch clock and the data path take the late derate: the data arrives as late as it plausibly could.
Capture side early
The capture clock takes the early derate: the capture edge comes as soon as it plausibly could.
One buffer, two speeds
root is on both clock paths, so it is late for the launch and early for the capture in the same check.

Read the diagram as text

clk port: 0.1 ns slew
root (clkbuf_4): common to both
bl (clkbuf_1): setup: late
bc (clkbuf_1): setup: early
ffl → u1 → u2: launch and data: late
ffc: capture: early

clk port → root (clkbuf_4): clock
root (clkbuf_4) → bl (clkbuf_1): clock
root (clkbuf_4) → bc (clkbuf_1): clock
bl (clkbuf_1) → ffl → u1 → u2: CLK
bc (clkbuf_1) → ffc: CLK
ffl → u1 → u2 → ffc: data

Each choice is pessimistic on purpose.

With ±5 % derates the setup slack at typical falls from 0.5262 to 0.5008 ns, and hold from 0.3730 to 0.3489 ns. The library's setup and hold times are not derated; -cell_check would do that.

The values ±5 % are illustrative. SKY130 publishes no derate recommendation that we know of, and this Liberty has no statistical variation tables. Flows with such tables replace flat derates with AOCV, which depends on the depth of the path, or POCV, which adds sigmas.

CPPR gives the common buffer back

The derates made root late for the launch and early for the capture at once: 0.1450 ns and 0.1312 ns. One buffer cannot be both at one edge. Clock reconvergence pessimism removal (CPPR; OpenSTA calls it CRPR) adds the difference back as a credit on the capture side.

Timing pathSetup with ±5 % derates and the CRPR credit

ffl → ffcsetup check, latest arrival3 cells

Clock latency
Cell delay
Setup time

Late launch clock
Through root and bl with the late derate: 0.2174 ns.
Early capture clock, then the credit
Through root and bc early: 0.1967 ns. The CRPR line adds 0.0138 ns, the two speeds of root.
Slack
0.5008 ns. Without the credit it would be 0.4870 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.2174 ns. Capture: clk rise edge at 1.0000 ns, latency 0.1967 ns, library setup time −0.1040 ns.

Arrival 0.6056 ns, required 1.1065 ns, slack 0.5008 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`ffl/CLK` → `ffl/Q`	dfxtp_1	fall	0.3094	0.5268	0.0345
	`ffl/Q` → `u1/A`	wire q1	fall	0.0000	0.5268	0.0345
2	`u1/A` → `u1/Y`	inv_1	rise	0.0438	0.5706	0.0308
	`u1/Y` → `u2/A`	wire n1	rise	0.0000	0.5706	0.0308
3	`u2/A` → `u2/Y`	nand2_1	fall	0.0350	0.6056	0.0251
	`u2/Y` → `ffc/D`	wire n2	fall	0.0000	0.6056	0.0251

The report

Startpoint: ffl (rising edge-triggered flip-flop clocked by clk)
Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0044    0.0334    0.1450    0.1450 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0334    0.0000    0.1450 ^ bl/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0724    0.2174 ^ bl/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl (net)
                    0.0353    0.0000    0.2174 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1)
     2    0.0044    0.0345    0.3094    0.5268 v ffl/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 q1 (net)
                    0.0345    0.0000    0.5268 v u1/A (sky130_fd_sc_hd__inv_1)
     1    0.0024    0.0308    0.0438    0.5706 ^ u1/Y (sky130_fd_sc_hd__inv_1)
                                                 n1 (net)
                    0.0308    0.0000    0.5706 ^ u2/A (sky130_fd_sc_hd__nand2_1)
     1    0.0017    0.0251    0.0350    0.6056 v u2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0251    0.0000    0.6056 v ffc/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.6056   data arrival time

                              1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock source latency
     1    0.0022    0.1000    0.0000    1.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0044    0.0334    0.1312    1.1312 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0334    0.0000    1.1312 ^ bc/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0655    1.1967 ^ bc/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cc (net)
                    0.0353    0.0000    1.1967 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0138    1.2105   clock reconvergence pessimism
                             -0.1040    1.1065   library setup time
                                        1.1065   data required time
-------------------------------------------------------------------------------------
                                        1.1065   data required time
                                       -0.6056   data arrival time
-------------------------------------------------------------------------------------
                                        0.5008   slack (MET)

Typical corner, set_timing_derate -early 0.95 -late 1.05; report_checks -format full_clock_expanded.

Nominal delay of the common segment
root with no derate: 0.1381 ns.
Late minus early
(1.05 − 0.95) × 0.1381 = 0.0138 ns.
The report
CRPR 0.0138 ns, the same to the printed digits.

For hold the credit appears with the opposite sign, on the required side: hold slack is 0.3489 ns with it. CPPR is on by default in OpenSTA. Without it, both checks would lose 0.0138 ns to a buffer that cannot be in two states.

The hold path with derates

Timing pathHold with ±5 % derates

ffl → ffchold check, earliest arrival2 cells

Clock latency
Cell delay
Hold time

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.1967 ns. Capture: clk rise edge at 0.0000 ns, latency 0.2174 ns, library hold time −0.0290 ns.

Arrival 0.5235 ns, required 0.1746 ns, slack 0.3489 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`ffl/CLK` → `ffl/Q`	dfxtp_1	fall	0.2799	0.4766	0.0345
	`ffl/Q` → `u2/B`	wire q1	fall	0.0000	0.4766	0.0345
2	`u2/B` → `u2/Y`	nand2_1	rise	0.0469	0.5235	0.0281
	`u2/Y` → `ffc/D`	wire n2	rise	0.0000	0.5235	0.0281

The report

Startpoint: ffl (rising edge-triggered flip-flop clocked by clk)
Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0044    0.0334    0.1312    0.1312 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0334    0.0000    0.1312 ^ bl/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0655    0.1967 ^ bl/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl (net)
                    0.0353    0.0000    0.1967 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1)
     2    0.0044    0.0345    0.2799    0.4766 v ffl/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 q1 (net)
                    0.0345    0.0000    0.4766 v u2/B (sky130_fd_sc_hd__nand2_1)
     1    0.0017    0.0281    0.0469    0.5235 ^ u2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0281    0.0000    0.5235 ^ ffc/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.5235   data arrival time

                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0044    0.0334    0.1450    0.1450 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0334    0.0000    0.1450 ^ bc/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0724    0.2174 ^ bc/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cc (net)
                    0.0353    0.0000    0.2174 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
                             -0.0138    0.2036   clock reconvergence pessimism
                             -0.0290    0.1746   library hold time
                                        0.1746   data required time
-------------------------------------------------------------------------------------
                                        0.1746   data required time
                                       -0.5235   data arrival time
-------------------------------------------------------------------------------------
                                        0.3489   slack (MET)

The same derated run, its hold path, with the CRPR credit on the required side.

Tools remove the pessimism for setup too, although launch and capture pass root at edges one period apart. Derates model variation that does not change from cycle to cycle. Jitter does, and it stays in the clock uncertainty of L2.4.

Asked in interviews

What is OCV and how do derates model it?
On-chip variation: the same cell differs across one die. Derates scale delays, late where a longer delay hurts the check and early where a shorter one does, so each check sees its worst plausible mix.
What is CPPR (CRPR)?
Clock reconvergence pessimism removal. Where launch and capture clocks share cells, derates make the shared part late and early at once; CPPR credits back late − early of that common segment.
Which corner do you check setup and hold at?
Setup where cells are slowest (slow process, low voltage, the slower temperature), hold where they are fastest (fast process, high voltage). Sign-off runs both checks at every corner.
What are AOCV and POCV?
Refinements of flat derates. AOCV makes the derate depend on path depth and distance; POCV (with LVF tables) gives each delay a sigma and adds them statistically.

Try it

This is ctree with ±5 % derates at the typical corner. Run it: setup 0.5008 ns, hold 0.3489 ns. Open Paths and find the CRPR line on the capture side.

Widen the derates to 0.9 and 1.1 and predict the new credit before you run. Then, in the netlist, give ffc its own clkbuf_4 straight from clk: the common segment shrinks to the port, and the credit goes with it.

STAOpenSTA in OpenROAD 26Q2 · sky130hd tt_025C_1v80 Liberty · simulator service

Edit the constraints or the netlist, then run

Expected: WNS 0.5008 ns worst minimum slack 0.3489 ns

Check yourself

Predict the outputThe derated ctree of Try it, with the period cut from 1.0 to 0.8 ns. What worst setup slack (WNS) does OpenSTA report, in ns?

create_clock -name clk -period 0.8 [get_ports clk]
set_propagated_clock [all_clocks]
set_input_transition 0.1 [get_ports clk]
set_timing_derate -early 0.95
set_timing_derate -late 1.05

Read the netlist: design.v

module ctree (clk, d, q);
  input clk;
  input d;
  output q;
  wire cr, cl, cc, q1, n1, n2;
  sky130_fd_sc_hd__clkbuf_4 root (.A(clk), .X(cr));
  sky130_fd_sc_hd__clkbuf_1 bl (.A(cr), .X(cl));
  sky130_fd_sc_hd__clkbuf_1 bc (.A(cr), .X(cc));
  sky130_fd_sc_hd__dfxtp_1 ffl (.CLK(cl), .D(d), .Q(q1));
  sky130_fd_sc_hd__inv_1 u1 (.A(q1), .Y(n1));
  sky130_fd_sc_hd__nand2_1 u2 (.A(n1), .B(q1), .Y(n2));
  sky130_fd_sc_hd__dfxtp_1 ffc (.CLK(cc), .D(n2), .Q(q));
endmodule

ConceptLaunch and capture clocks share 0.20 ns of buffers. The derates are 0.9 early and 1.1 late. What credit does CPPR give?

0.040 ns0.220 ns0.080 ns0.020 ns

ConceptFor a hold check, which delays does the tool derate late?

The launch clock path and the data pathThe capture clock path onlyAll three paths, by the same late factorThe data path only; clocks are never derated

ConceptWhy are setup and hold signed off at different corners?

Each corner's file is only valid for one kind of checkHold needs high temperature, and setup needs low voltage onlySetup suffers when cells are slow, hold when they are fastLiberty files hold setup tables or hold tables, never both

ConceptSupply noise makes root's delay change by a few picoseconds from one cycle to the next. Where should the SDC account for it?

In a larger late derate on root, so setup sees itNowhere: CPPR removes all variation on a common bufferIn another corner, since supply noise is a voltage changeIn the clock uncertainty, which CPPR never credits back

Remember

A corner is one process, voltage and temperature with its own Liberty; setup is worst at slow corners, hold at fast ones.
Which temperature is slower is measured, not assumed: here the cold slow corner is slower.
Derates model on-chip variation: launch clock and data late, capture clock early for setup, and the reverse for hold.
CPPR credits late − early delay of the clock segment launch and capture share.