Input and output delays

Constrain the ports of a block with input and output delays, a driving cell and a load, and read the paths that cross its boundary.

Lesson: L2.7
Time: 30 min
Runs on: OpenROAD
Check: 5 questions

The MAC met a 5 ns clock when it was timed alone with only its clock. In the chip, its enable en came from a controller whose own logic used 4 ns of the cycle. The path from en into the MAC's registers had never been timed, and it missed the edge by 0.3830 ns.

Timing pathen into the MAC, with the controller's delayset_input_delay 4 puts the arrival at the port 4 ns after the edge; a buf_4 drives the port.

en → _827_setup check, latest arrival4 cells

Clock latency
Cell delay
Input delay
Setup time

Outside the block
The controller's flop and logic take 4 ns, written as the input delay. The buf_4 that drives en then charges 0.1868 pF on 69 pins: 0.3589 ns.
Inside the MAC
The MAC's own gates add 0.9227 ns, starting at the slow slew the port left.
Violated
Arrival 5.2816 ns, required 4.8985 ns: slack -0.3830 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 5.0000 ns, latency 0.0000 ns, library setup time −0.1015 ns.

Arrival 5.2816 ns, required 4.8985 ns, slack −0.3830 ns (violated).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
	`en` → `_738_/B1`	wire en	rise	0.0000	4.3589	0.5105
1	`_738_/B1` → `_738_/Y`	o21ai_0	fall	0.1989	4.5577	0.1542
	`_738_/Y` → `_740_/B1`	wire _103_	fall	0.0000	4.5577	0.1542
2	`_740_/B1` → `_740_/Y`	a211oi_1	rise	0.4381	4.9959	0.4445
	`_740_/Y` → `_742_/C`	wire _105_	rise	0.0000	4.9959	0.4445
3	`_742_/C` → `_742_/Y`	nand3_1	fall	0.1474	5.1433	0.1059
	`_742_/Y` → `_748_/B`	wire _107_	fall	0.0000	5.1433	0.1059
4	`_748_/B` → `_748_/Y`	xnor2_1	fall	0.1383	5.2816	0.0445
	`_748_/Y` → `_827_/D`	wire _048_	fall	0.0000	5.2816	0.0445

The report

Startpoint: en (input port clocked by clk)
Endpoint: _827_ (rising edge-triggered flip-flop clocked by clk)
Path Group: in2reg
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                              4.0000    4.0000 ^ input external delay
    69    0.1868    0.5105    0.3589    4.3589 ^ en (in)
                                                 en (net)
                    0.5105    0.0000    4.3589 ^ _738_/B1 (sky130_fd_sc_hd__o21ai_0)
     2    0.0044    0.1542    0.1989    4.5577 v _738_/Y (sky130_fd_sc_hd__o21ai_0)
                                                 _103_ (net)
                    0.1542    0.0000    4.5577 v _740_/B1 (sky130_fd_sc_hd__a211oi_1)
     4    0.0119    0.4445    0.4381    4.9959 ^ _740_/Y (sky130_fd_sc_hd__a211oi_1)
                                                 _105_ (net)
                    0.4445    0.0000    4.9959 ^ _742_/C (sky130_fd_sc_hd__nand3_1)
     1    0.0045    0.1059    0.1474    5.1433 v _742_/Y (sky130_fd_sc_hd__nand3_1)
                                                 _107_ (net)
                    0.1059    0.0000    5.1433 v _748_/B (sky130_fd_sc_hd__xnor2_1)
     1    0.0019    0.0445    0.1383    5.2816 v _748_/Y (sky130_fd_sc_hd__xnor2_1)
                                                 _048_ (net)
                    0.0445    0.0000    5.2816 v _827_/D (sky130_fd_sc_hd__dfrtp_1)
                                        5.2816   data arrival time

                    0.1000    5.0000    5.0000   clock clk (rise edge)
                              0.0000    5.0000   clock network delay (ideal)
                              0.0000    5.0000   clock reconvergence pessimism
                                        5.0000 ^ _827_/CLK (sky130_fd_sc_hd__dfrtp_1)
                             -0.1015    4.8985   library setup time
                                        4.8985   data required time
-------------------------------------------------------------------------------------
                                        4.8985   data required time
                                       -5.2816   data arrival time
-------------------------------------------------------------------------------------
                                       -0.3830   slack (VIOLATED)

OpenSTA 3.1.0, mac8 (447 cells) on the sky130 tt library, ideal 5 ns clock, no wires.

Neither block's report showed the failure, because each one assumed the whole cycle for its half of the path.

Half a path on each side of the port

A path that crosses a block's boundary starts or ends outside the block. The block's timing run sees only its own half, so the SDC must describe the other half.

One path through three blocksArrows are data. The two outer halves are what the input and output delays stand for.

Input delay
set_input_delay is the time from the clock edge to the signal's arrival at the port: the outside flop's clock-to-Q plus the outside logic.
Inside the block
The block's own run times the rest, from the port to its registers, against the next edge.
Output delay
set_output_delay is how much of the cycle the outside still needs after the port: its logic plus its flop's setup.

Read the diagram as text

Controller flop: launches on clk
en port: arrives input delay after the edge
MAC registers: capture, then launch
acc port: needed output delay before the edge
Next block's flop: captures on clk

Controller flop → en port: input delay
en port → MAC registers: block logic
MAC registers → acc port: clock-to-Q
acc port → Next block's flop: output delay

Both delays are measured from the same clock edge the block uses.

SDC line	Path it shapes	Term in the check
`set_input_delay -max` D_in	input to register, setup	arrival starts at D_in
`set_input_delay -min` D_in	input to register, hold	earliest arrival starts at D_in
`set_output_delay -max` D_out	register to output, setup	required = T − D_out
`set_output_delay -min` D_out	register to output, hold	required = −D_out
both on one path	input to output	the block gets T − D_in − D_out

Without -max or -min, one value sets both. T is the clock period.

For a register-to-output path, the output delay comes off the cycle. With 1 ns of output delay the MAC's acc ports must be valid by 4.0000 ns.

Timing pathAn acc bit leaving the MACA result flop drives the acc port; set_output_delay -max 1 takes 1 ns from the required time.

_821_ → acc[13]setup check, latest arrival1 cell

Clock latency
Cell delay
Setup time

Clock-to-Q only
The flop's output reaches the port at 0.4571 ns.
The outside needs its share
5 ns minus the 1 ns output delay: required at 4.0000 ns.
Met
Slack 3.5429 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 5.0000 ns, latency 0.0000 ns, library setup time −1.0000 ns.

Arrival 0.4571 ns, required 4.0000 ns, slack 3.5429 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`_821_/CLK` → `_821_/Q`	dfrtp_1	fall	0.4571	0.4571	0.1193
	`_821_/Q` → `acc[13]`	wire acc[13]	fall	0.0000	0.4571	0.1193

The report

Startpoint: _821_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: acc[13] (output port clocked by clk)
Path Group: reg2out
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                    0.1000    0.0000    0.0000 ^ _821_/CLK (sky130_fd_sc_hd__dfrtp_1)
     5    0.0211    0.1193    0.4571    0.4571 v _821_/Q (sky130_fd_sc_hd__dfrtp_1)
                                                 acc[13] (net)
                    0.1193    0.0000    0.4571 v acc[13] (out)
                                        0.4571   data arrival time

                    0.1000    5.0000    5.0000   clock clk (rise edge)
                              0.0000    5.0000   clock network delay (ideal)
                              0.0000    5.0000   clock reconvergence pessimism
                             -1.0000    4.0000   output external delay
                                        4.0000   data required time
-------------------------------------------------------------------------------------
                                        4.0000   data required time
                                       -0.4571   data arrival time
-------------------------------------------------------------------------------------
                                        3.5429   slack (MET)

The same run as the opening figure, path group reg2out.

The port needs a driver and a load

Without set_driving_cell, the tool treats an input as a perfect source: zero delay and zero slew at the port. The en port drives 69 pins, which no real driver does instantly. With a buf_4 behind it, the report adds a port line of 0.3589 ns and a 0.5105 ns slew.

en path	Port delay	Port slew	Inside the MAC	Slack
no driving cell	0.0000 ns	0.0000 ns	0.7691 ns	0.1294 ns
`buf_4` driving	0.3589 ns	0.5105 ns	1.2816 ns	-0.3830 ns

Both runs use the same 4 ns input delay. The slow slew also slows the first gate after the port.

The en path without a driving cell

Timing pathen into the MAC, ideal input

en → _827_setup check, latest arrival4 cells

Clock latency
Cell delay
Input delay
Setup time

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 5.0000 ns, latency 0.0000 ns, library setup time −0.1015 ns.

Arrival 4.7691 ns, required 4.8985 ns, slack 0.1294 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
	`en` → `_738_/B1`	wire en	rise	0.0000	4.0000	0.0000
1	`_738_/B1` → `_738_/Y`	o21ai_0	fall	0.0722	4.0722	0.0807
	`_738_/Y` → `_740_/B1`	wire _103_	fall	0.0000	4.0722	0.0807
2	`_740_/B1` → `_740_/Y`	a211oi_1	rise	0.4113	4.4834	0.4445
	`_740_/Y` → `_742_/C`	wire _105_	rise	0.0000	4.4834	0.4445
3	`_742_/C` → `_742_/Y`	nand3_1	fall	0.1474	4.6308	0.1059
	`_742_/Y` → `_748_/B`	wire _107_	fall	0.0000	4.6308	0.1059
4	`_748_/B` → `_748_/Y`	xnor2_1	fall	0.1383	4.7691	0.0445
	`_748_/Y` → `_827_/D`	wire _048_	fall	0.0000	4.7691	0.0445

The report

Startpoint: en (input port clocked by clk)
Endpoint: _827_ (rising edge-triggered flip-flop clocked by clk)
Path Group: in2reg
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                              4.0000    4.0000 ^ input external delay
    69    0.1868    0.0000    0.0000    4.0000 ^ en (in)
                                                 en (net)
                    0.0000    0.0000    4.0000 ^ _738_/B1 (sky130_fd_sc_hd__o21ai_0)
     2    0.0044    0.0807    0.0722    4.0722 v _738_/Y (sky130_fd_sc_hd__o21ai_0)
                                                 _103_ (net)
                    0.0807    0.0000    4.0722 v _740_/B1 (sky130_fd_sc_hd__a211oi_1)
     4    0.0119    0.4445    0.4113    4.4834 ^ _740_/Y (sky130_fd_sc_hd__a211oi_1)
                                                 _105_ (net)
                    0.4445    0.0000    4.4834 ^ _742_/C (sky130_fd_sc_hd__nand3_1)
     1    0.0045    0.1059    0.1474    4.6308 v _742_/Y (sky130_fd_sc_hd__nand3_1)
                                                 _107_ (net)
                    0.1059    0.0000    4.6308 v _748_/B (sky130_fd_sc_hd__xnor2_1)
     1    0.0019    0.0445    0.1383    4.7691 v _748_/Y (sky130_fd_sc_hd__xnor2_1)
                                                 _048_ (net)
                    0.0445    0.0000    4.7691 v _827_/D (sky130_fd_sc_hd__dfrtp_1)
                                        4.7691   data arrival time

                    0.1000    5.0000    5.0000   clock clk (rise edge)
                              0.0000    5.0000   clock network delay (ideal)
                              0.0000    5.0000   clock reconvergence pessimism
                                        5.0000 ^ _827_/CLK (sky130_fd_sc_hd__dfrtp_1)
                             -0.1015    4.8985   library setup time
                                        4.8985   data required time
-------------------------------------------------------------------------------------
                                        4.8985   data required time
                                       -4.7691   data arrival time
-------------------------------------------------------------------------------------
                                        0.1294   slack (MET)

The same SDC without set_driving_cell.

Pick the cell the real driver will be. A buf_4 is a fair guess for a signal from another block. An I/O pad driver is much stronger, and a small gate deep in a neighbour's logic much weaker, so a wrong guess moves every input path.

The driving cell decides whether this path passes. set_input_transition is the simpler form: a fixed slew, with no load-dependent delay. On the output side, set_load 0.01 puts 10 fF on each acc port, the input pins and wire of the next block. Without it the result flops drive almost nothing and look faster than they are.

Budgets, minimum delays and virtual clocks

The 4 ns was the controller's number, not the MAC's choice. Budgets are agreed between neighbours. A common start gives each side of a boundary a share of the period, then replaces the shares with real numbers as the blocks are built. Here the en path meets timing for any input delay up to 3.6170 ns.

Minimum delays feed the hold checks. A -min input delay is the earliest the input can change. A -min output delay is the outside hold requirement, written with a sign flip. If the next block's flop needs 0.3 ns of hold and 0.1 ns of logic sits before it, the output must not change until 0.2 ns after the edge: -min -0.2.

Timing pathHold at an acc portset_output_delay -min -0.2: the required time moves to +0.2 ns.

_827_ → acc[19]hold check, earliest arrival1 cell

Clock latency
Cell delay
Hold time

Hold after the edge
Required after 0.2000 ns: the negative minimum delay is a positive hold time outside.
Met
The flop's clock-to-Q keeps the old value until 0.4121 ns: slack 0.2121 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 0.0000 ns, latency 0.0000 ns, library hold time 0.2000 ns.

Arrival 0.4121 ns, required 0.2000 ns, slack 0.2121 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`_827_/CLK` → `_827_/Q`	dfrtp_1	rise	0.4121	0.4121	0.1416
	`_827_/Q` → `acc[19]`	wire acc[19]	rise	0.0000	0.4121	0.1416

The report

Startpoint: _827_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: acc[19] (output port clocked by clk)
Path Group: reg2out
Path Type: min

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                    0.1000    0.0000    0.0000 ^ _827_/CLK (sky130_fd_sc_hd__dfrtp_1)
     2    0.0147    0.1416    0.4121    0.4121 ^ _827_/Q (sky130_fd_sc_hd__dfrtp_1)
                                                 acc[19] (net)
                    0.1416    0.0000    0.4121 ^ acc[19] (out)
                                        0.4121   data arrival time

                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                              0.0000    0.0000   clock reconvergence pessimism
                              0.2000    0.2000   output external delay
                                        0.2000   data required time
-------------------------------------------------------------------------------------
                                        0.2000   data required time
                                       -0.4121   data arrival time
-------------------------------------------------------------------------------------
                                        0.2121   slack (MET)

The same run, the hold path of group reg2out.

An input-to-output path through a block gets what is left of the period after both delays. Such feed-throughs are often the first boundary paths to fail, because two neighbours have already taken their shares.

A virtual clock is a create_clock with a name and a period but no source: create_clock -name vclk -period 5. It stands for a clock outside the block. Use it in set_input_delay -clock vclk when the outside launch clock differs from the block's, or when a port has no register clock of its own, as on a purely combinational path.

Asked in interviews

What do set_input_delay and set_output_delay model?
The part of a boundary path outside the block. Input delay: when the signal arrives after the clock edge. Output delay: how much time the outside needs before the capture edge.
How do you budget I/O delays between blocks?
Start with an agreed share of the period on each side of every boundary, then replace the shares with the neighbours' real numbers as they are timed. Re-check the full path at the top level.
What is a virtual clock?
A clock with no source in the design. It names the outside clock that launches or captures an I/O path, so I/O delays can refer to it.
What happens if you forget to constrain I/O?
Input-to-register and register-to-output paths are not timed at all. check_setup lists the ports without delays, and the block can pass alone while the chip-level path fails.

Try it

This is the SDC of the opening figure. Run it: WNS -0.3830 ns on the en path, WHS 0.2121 ns at an acc port.

Lower the input delay to 3.6170 ns and the en path just meets. Then delete the set_driving_cell line and see the port line drop to zero. Last, delete both set_input_delay and set_output_delay lines: Output lists every data port as missing its delay.

STAOpenSTA in OpenROAD 26Q2 · sky130hd tt_025C_1v80 Liberty · simulator service

Edit the constraints, then run them

Expected: WNS -0.383 ns worst minimum slack 0.2121 ns

Read the netlist: mac.v (the bundled design mac8)

/* Generated by Yosys 0.70+290 (git sha1 e8968a4f7, Release, Clang /usr/bin/clang++ 21.1.8) */

module mac(clk, rst_n, en, a, b, acc);
  input clk;
  wire clk;
  input rst_n;
  wire rst_n;
  input en;
  wire en;
  input [7:0] a;
  wire [7:0] a;
  input [7:0] b;
  wire [7:0] b;
  output [19:0] acc;
  wire [19:0] acc;
  wire _000_;
  wire _001_;
  wire _002_;
  wire _003_;
  wire _004_;
  wire _005_;
  wire _006_;
  wire _007_;
  wire _008_;
  wire _009_;
  wire _010_;
  wire _011_;
  wire _012_;
  wire _013_;
  wire _014_;
  wire _015_;
  wire _016_;
  wire _017_;
  wire _018_;
  wire _019_;
  wire _020_;
  wire _021_;
  wire _022_;
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  wire _047_;
  wire _048_;
  wire _049_;
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  wire _308_;
  wire _309_;
  wire _310_;
  wire _311_;
  wire _312_;
  wire _313_;
  wire _314_;
  wire _315_;
  wire _316_;
  wire _317_;
  wire _318_;
  wire _319_;
  wire _320_;
  wire _321_;
  wire _322_;
  wire _323_;
  wire _324_;
  wire _325_;
  wire _326_;
  wire _327_;
  wire _328_;
  wire _329_;
  wire _330_;
  wire _331_;
  wire _332_;
  wire _333_;
  wire _334_;
  wire _335_;
  wire _336_;
  wire _337_;
  wire _338_;
  wire _339_;
  wire _340_;
  wire _341_;
  wire _342_;
  wire _343_;
  wire _344_;
  wire _345_;
  wire _346_;
  wire _347_;
  wire _348_;
  wire _349_;
  wire _350_;
  wire _351_;
  wire _352_;
  wire _353_;
  wire _354_;
  wire _355_;
  wire _356_;
  wire _357_;
  wire _358_;
  wire _359_;
  wire _360_;
  wire _361_;
  wire _362_;
  wire _363_;
  wire _364_;
  wire _365_;
  wire _366_;
  wire _367_;
  wire _368_;
  wire _369_;
  wire _370_;
  wire _371_;
  wire _372_;
  wire _373_;
  wire _374_;
  wire _375_;
  wire _376_;
  wire _377_;
  wire _378_;
  wire _379_;
  wire _380_;
  wire _381_;
  wire _382_;
  wire _383_;
  wire _384_;
  wire _385_;
  wire _386_;
  wire _387_;
  wire _388_;
  wire _389_;
  wire _390_;
  wire _391_;
  wire _392_;
  wire _393_;
  wire _394_;
  wire \p[0] ;
  wire \p[10] ;
  wire \p[11] ;
  wire \p[12] ;
  wire \p[13] ;
  wire \p[14] ;
  wire \p[15] ;
  wire \p[1] ;
  wire \p[2] ;
  wire \p[3] ;
  wire \p[4] ;
  wire \p[5] ;
  wire \p[6] ;
  wire \p[7] ;
  wire \p[8] ;
  wire \p[9] ;
  wire \ra[0] ;
  wire \ra[1] ;
  wire \ra[2] ;
  wire \ra[3] ;
  wire \ra[4] ;
  wire \ra[5] ;
  wire \ra[6] ;
  wire \ra[7] ;
  wire \rb[0] ;
  wire \rb[1] ;
  wire \rb[2] ;
  wire \rb[3] ;
  wire \rb[4] ;
  wire \rb[5] ;
  wire \rb[6] ;
  wire \rb[7] ;
  sky130_fd_sc_hd__clkinv_1 _395_ (
    .A(en),
    .Y(_052_)
  );
  sky130_fd_sc_hd__clkinv_1 _396_ (
    .A(acc[16]),
    .Y(_053_)
  );
  sky130_fd_sc_hd__xnor2_1 _397_ (
    .A(acc[12]),
    .B(\p[12] ),
    .Y(_061_)
  );
  sky130_fd_sc_hd__xor3_1 _398_ (
    .A(_112_),
    .B(_145_),
    .C(_146_),
    .X(_148_)
  );
  sky130_fd_sc_hd__nand2_1 _399_ (
    .A(_144_),
    .B(_148_),
    .Y(_149_)
  );
  sky130_fd_sc_hd__nand3_1 _400_ (
    .A(\ra[7] ),
    .B(\rb[2] ),
    .C(_149_),
    .Y(_150_)
  );
  sky130_fd_sc_hd__xnor2_1 _401_ (
    .A(_115_),
    .B(_116_),
    .Y(_151_)
  );
  sky130_fd_sc_hd__nand2_1 _402_ (
    .A(\rb[7] ),
    .B(\ra[3] ),
    .Y(_152_)
  );
  sky130_fd_sc_hd__maj3_1 _403_ (
    .A(_112_),
    .B(_145_),
    .C(_146_),
    .X(_153_)
  );
  sky130_fd_sc_hd__nand2_1 _404_ (
    .A(\ra[4] ),
    .B(\rb[6] ),
    .Y(_154_)
  );
  sky130_fd_sc_hd__xnor2_1 _405_ (
    .A(_153_),
    .B(_154_),
    .Y(_155_)
  );
  sky130_fd_sc_hd__xnor2_1 _406_ (
    .A(_152_),
    .B(_155_),
    .Y(_156_)
  );
  sky130_fd_sc_hd__maj3_1 _407_ (
    .A(_150_),
    .B(_151_),
    .C(_156_),
    .X(_157_)
  );
  sky130_fd_sc_hd__clkinv_1 _408_ (
    .A(_061_),
    .Y(_062_)
  );
  sky130_fd_sc_hd__xnor2_1 _409_ (
    .A(_120_),
    .B(_124_),
    .Y(_158_)
  );
  sky130_fd_sc_hd__nor2b_1 _410_ (
    .A(_157_),
    .B_N(_158_),
    .Y(_159_)
  );
  sky130_fd_sc_hd__maj3_1 _411_ (
    .A(_152_),
    .B(_153_),
    .C(_154_),
    .X(_160_)
  );
  sky130_fd_sc_hd__xnor2_1 _412_ (
    .A(_157_),
    .B(_158_),
    .Y(_161_)
  );
  sky130_fd_sc_hd__nor2b_1 _413_ (
    .A(_160_),
    .B_N(_161_),
    .Y(_162_)
  );
  sky130_fd_sc_hd__xor2_1 _414_ (
    .A(_135_),
    .B(_136_),
    .X(_163_)
  );
  sky130_fd_sc_hd__o21a_1 _415_ (
    .A1(_159_),
    .A2(_162_),
    .B1(_163_),
    .X(_164_)
  );
  sky130_fd_sc_hd__nand2_1 _416_ (
    .A(\ra[7] ),
    .B(\rb[1] ),
    .Y(_165_)
  );
  sky130_fd_sc_hd__and2_0 _417_ (
    .A(\ra[6] ),
    .B(\rb[0] ),
    .X(_166_)
  );
  sky130_fd_sc_hd__nand2_1 _418_ (
    .A(\ra[7] ),
    .B(\rb[0] ),
    .Y(_167_)
  );
  sky130_fd_sc_hd__and2_0 _419_ (
    .A(acc[11]),
    .B(\p[11] ),
    .X(_063_)
  );
  sky130_fd_sc_hd__nand2_1 _420_ (
    .A(\ra[5] ),
    .B(\rb[2] ),
    .Y(_168_)
  );
  sky130_fd_sc_hd__maj3_1 _421_ (
    .A(_144_),
    .B(_167_),
    .C(_168_),
    .X(_169_)
  );
  sky130_fd_sc_hd__nand2_1 _422_ (
    .A(\ra[6] ),
    .B(\rb[2] ),
    .Y(_170_)
  );
  sky130_fd_sc_hd__xnor2_1 _423_ (
    .A(_165_),
    .B(_170_),
    .Y(_171_)
  );
  sky130_fd_sc_hd__nand2_1 _424_ (
    .A(\ra[3] ),
    .B(\rb[5] ),
    .Y(_172_)
  );
  sky130_fd_sc_hd__nand2_1 _425_ (
    .A(\ra[4] ),
    .B(\rb[4] ),
    .Y(_173_)
  );
  sky130_fd_sc_hd__nand2_1 _426_ (
    .A(\ra[4] ),
    .B(\rb[3] ),
    .Y(_174_)
  );
  sky130_fd_sc_hd__xor3_1 _427_ (
    .A(_147_),
    .B(_172_),
    .C(_173_),
    .X(_175_)
  );
  sky130_fd_sc_hd__maj3_1 _428_ (
    .A(_169_),
    .B(_171_),
    .C(_175_),
    .X(_176_)
  );
  sky130_fd_sc_hd__nand3_1 _429_ (
    .A(\ra[7] ),
    .B(\rb[2] ),
    .C(_144_),
    .Y(_177_)
  );
  sky130_fd_sc_hd__nand2_1 _430_ (
    .A(acc[11]),
    .B(\p[11] ),
    .Y(_064_)
  );
  sky130_fd_sc_hd__xnor2_1 _431_ (
    .A(_148_),
    .B(_177_),
    .Y(_178_)
  );
  sky130_fd_sc_hd__nand2_1 _432_ (
    .A(\rb[7] ),
    .B(\ra[2] ),
    .Y(_179_)
  );
  sky130_fd_sc_hd__maj3_1 _433_ (
    .A(_147_),
    .B(_172_),
    .C(_173_),
    .X(_180_)
  );
  sky130_fd_sc_hd__nand2_1 _434_ (
    .A(\ra[3] ),
    .B(\rb[6] ),
    .Y(_181_)
  );
  sky130_fd_sc_hd__xnor2_1 _435_ (
    .A(_180_),
    .B(_181_),
    .Y(_182_)
  );
  sky130_fd_sc_hd__xnor2_1 _436_ (
    .A(_179_),
    .B(_182_),
    .Y(_183_)
  );
  sky130_fd_sc_hd__xnor2_1 _437_ (
    .A(_176_),
    .B(_178_),
    .Y(_184_)
  );
  sky130_fd_sc_hd__maj3_1 _438_ (
    .A(_176_),
    .B(_178_),
    .C(_183_),
    .X(_185_)
  );
  sky130_fd_sc_hd__xor3_1 _439_ (
    .A(_150_),
    .B(_151_),
    .C(_156_),
    .X(_186_)
  );
  sky130_fd_sc_hd__maj3_1 _440_ (
    .A(_179_),
    .B(_180_),
    .C(_181_),
    .X(_187_)
  );
  sky130_fd_sc_hd__nor2_1 _441_ (
    .A(acc[11]),
    .B(\p[11] ),
    .Y(_065_)
  );
  sky130_fd_sc_hd__xor2_1 _442_ (
    .A(_185_),
    .B(_186_),
    .X(_188_)
  );
  sky130_fd_sc_hd__maj3_1 _443_ (
    .A(_185_),
    .B(_186_),
    .C(_187_),
    .X(_189_)
  );
  sky130_fd_sc_hd__xor2_1 _444_ (
    .A(_160_),
    .B(_161_),
    .X(_190_)
  );
  sky130_fd_sc_hd__nor2_1 _445_ (
    .A(_189_),
    .B(_190_),
    .Y(_191_)
  );
  sky130_fd_sc_hd__nand2_1 _446_ (
    .A(\ra[5] ),
    .B(\rb[0] ),
    .Y(_192_)
  );
  sky130_fd_sc_hd__and2_0 _447_ (
    .A(\ra[5] ),
    .B(\rb[1] ),
    .X(_193_)
  );
  sky130_fd_sc_hd__and2_0 _448_ (
    .A(\ra[4] ),
    .B(\rb[2] ),
    .X(_194_)
  );
  sky130_fd_sc_hd__maj3_1 _449_ (
    .A(_166_),
    .B(_193_),
    .C(_194_),
    .X(_195_)
  );
  sky130_fd_sc_hd__xnor3_1 _450_ (
    .A(_144_),
    .B(_167_),
    .C(_168_),
    .X(_196_)
  );
  sky130_fd_sc_hd__nand2_1 _451_ (
    .A(\ra[2] ),
    .B(\rb[5] ),
    .Y(_197_)
  );
  sky130_fd_sc_hd__clkinv_1 _452_ (
    .A(_065_),
    .Y(_066_)
  );
  sky130_fd_sc_hd__nand2_1 _453_ (
    .A(\ra[3] ),
    .B(\rb[4] ),
    .Y(_198_)
  );
  sky130_fd_sc_hd__nand2_1 _454_ (
    .A(\ra[3] ),
    .B(\rb[3] ),
    .Y(_199_)
  );
  sky130_fd_sc_hd__xnor3_1 _455_ (
    .A(_174_),
    .B(_197_),
    .C(_198_),
    .X(_200_)
  );
  sky130_fd_sc_hd__maj3_1 _456_ (
    .A(_195_),
    .B(_196_),
    .C(_200_),
    .X(_201_)
  );
  sky130_fd_sc_hd__xnor3_1 _457_ (
    .A(_169_),
    .B(_171_),
    .C(_175_),
    .X(_202_)
  );
  sky130_fd_sc_hd__nand2_1 _458_ (
    .A(\rb[7] ),
    .B(\ra[1] ),
    .Y(_203_)
  );
  sky130_fd_sc_hd__maj3_1 _459_ (
    .A(_174_),
    .B(_197_),
    .C(_198_),
    .X(_204_)
  );
  sky130_fd_sc_hd__nand2_1 _460_ (
    .A(\ra[2] ),
    .B(\rb[6] ),
    .Y(_205_)
  );
  sky130_fd_sc_hd__xor2_1 _461_ (
    .A(_204_),
    .B(_205_),
    .X(_206_)
  );
  sky130_fd_sc_hd__xnor2_1 _462_ (
    .A(_203_),
    .B(_206_),
    .Y(_207_)
  );
  sky130_fd_sc_hd__and2_0 _463_ (
    .A(acc[10]),
    .B(\p[10] ),
    .X(_067_)
  );
  sky130_fd_sc_hd__xor2_1 _464_ (
    .A(_201_),
    .B(_202_),
    .X(_208_)
  );
  sky130_fd_sc_hd__maj3_1 _465_ (
    .A(_201_),
    .B(_202_),
    .C(_207_),
    .X(_209_)
  );
  sky130_fd_sc_hd__xnor2_1 _466_ (
    .A(_183_),
    .B(_184_),
    .Y(_210_)
  );
  sky130_fd_sc_hd__nand2b_1 _467_ (
    .A_N(_210_),
    .B(_209_),
    .Y(_211_)
  );
  sky130_fd_sc_hd__maj3_1 _468_ (
    .A(_203_),
    .B(_204_),
    .C(_205_),
    .X(_212_)
  );
  sky130_fd_sc_hd__xnor2_1 _469_ (
    .A(_209_),
    .B(_210_),
    .Y(_213_)
  );
  sky130_fd_sc_hd__nand2b_1 _470_ (
    .A_N(_212_),
    .B(_213_),
    .Y(_214_)
  );
  sky130_fd_sc_hd__and2_0 _471_ (
    .A(_211_),
    .B(_214_),
    .X(_215_)
  );
  sky130_fd_sc_hd__xor2_1 _472_ (
    .A(_187_),
    .B(_188_),
    .X(_216_)
  );
  sky130_fd_sc_hd__nor2_1 _473_ (
    .A(_215_),
    .B(_216_),
    .Y(_217_)
  );
  sky130_fd_sc_hd__nor2_1 _474_ (
    .A(acc[10]),
    .B(\p[10] ),
    .Y(_068_)
  );
  sky130_fd_sc_hd__nand2_1 _475_ (
    .A(\ra[4] ),
    .B(\rb[1] ),
    .Y(_218_)
  );
  sky130_fd_sc_hd__and2_0 _476_ (
    .A(\ra[4] ),
    .B(\rb[0] ),
    .X(_219_)
  );
  sky130_fd_sc_hd__nand2_1 _477_ (
    .A(\ra[3] ),
    .B(\rb[2] ),
    .Y(_220_)
  );
  sky130_fd_sc_hd__maj3_1 _478_ (
    .A(_192_),
    .B(_218_),
    .C(_220_),
    .X(_221_)
  );
  sky130_fd_sc_hd__xnor3_1 _479_ (
    .A(_166_),
    .B(_193_),
    .C(_194_),
    .X(_222_)
  );
  sky130_fd_sc_hd__nand2_1 _480_ (
    .A(\ra[1] ),
    .B(\rb[5] ),
    .Y(_223_)
  );
  sky130_fd_sc_hd__nand2_1 _481_ (
    .A(\ra[2] ),
    .B(\rb[4] ),
    .Y(_224_)
  );
  sky130_fd_sc_hd__nand2_1 _482_ (
    .A(\ra[2] ),
    .B(\rb[3] ),
    .Y(_225_)
  );
  sky130_fd_sc_hd__xor3_1 _483_ (
    .A(_199_),
    .B(_223_),
    .C(_224_),
    .X(_226_)
  );
  sky130_fd_sc_hd__maj3_1 _484_ (
    .A(_221_),
    .B(_222_),
    .C(_226_),
    .X(_227_)
  );
  sky130_fd_sc_hd__nor2_1 _485_ (
    .A(_067_),
    .B(_068_),
    .Y(_069_)
  );
  sky130_fd_sc_hd__xnor3_1 _486_ (
    .A(_195_),
    .B(_196_),
    .C(_200_),
    .X(_228_)
  );
  sky130_fd_sc_hd__nand2_1 _487_ (
    .A(\rb[7] ),
    .B(\ra[0] ),
    .Y(_229_)
  );
  sky130_fd_sc_hd__maj3_1 _488_ (
    .A(_199_),
    .B(_223_),
    .C(_224_),
    .X(_230_)
  );
  sky130_fd_sc_hd__nand2_1 _489_ (
    .A(\ra[1] ),
    .B(\rb[6] ),
    .Y(_231_)
  );
  sky130_fd_sc_hd__xor3_1 _490_ (
    .A(_229_),
    .B(_230_),
    .C(_231_),
    .X(_232_)
  );
  sky130_fd_sc_hd__xnor2_1 _491_ (
    .A(_227_),
    .B(_228_),
    .Y(_233_)
  );
  sky130_fd_sc_hd__maj3_1 _492_ (
    .A(_227_),
    .B(_228_),
    .C(_232_),
    .X(_234_)
  );
  sky130_fd_sc_hd__xnor2_1 _493_ (
    .A(_207_),
    .B(_208_),
    .Y(_235_)
  );
  sky130_fd_sc_hd__nor2_1 _494_ (
    .A(_234_),
    .B(_235_),
    .Y(_236_)
  );
  sky130_fd_sc_hd__maj3_1 _495_ (
    .A(_229_),
    .B(_230_),
    .C(_231_),
    .X(_237_)
  );
  sky130_fd_sc_hd__and2_0 _496_ (
    .A(acc[9]),
    .B(\p[9] ),
    .X(_070_)
  );
  sky130_fd_sc_hd__xor3_1 _497_ (
    .A(_207_),
    .B(_208_),
    .C(_234_),
    .X(_238_)
  );
  sky130_fd_sc_hd__nor2_1 _498_ (
    .A(_237_),
    .B(_238_),
    .Y(_239_)
  );
  sky130_fd_sc_hd__nor2_1 _499_ (
    .A(_236_),
    .B(_239_),
    .Y(_240_)
  );
  sky130_fd_sc_hd__xnor2_1 _500_ (
    .A(_212_),
    .B(_213_),
    .Y(_241_)
  );
  sky130_fd_sc_hd__o21ai_0 _501_ (
    .A1(_236_),
    .A2(_239_),
    .B1(_241_),
    .Y(_242_)
  );
  sky130_fd_sc_hd__and2_0 _502_ (
    .A(\ra[3] ),
    .B(\rb[1] ),
    .X(_243_)
  );
  sky130_fd_sc_hd__nand2_1 _503_ (
    .A(\ra[3] ),
    .B(\rb[0] ),
    .Y(_244_)
  );
  sky130_fd_sc_hd__and2_0 _504_ (
    .A(\ra[2] ),
    .B(\rb[2] ),
    .X(_245_)
  );
  sky130_fd_sc_hd__maj3_1 _505_ (
    .A(_219_),
    .B(_243_),
    .C(_245_),
    .X(_246_)
  );
  sky130_fd_sc_hd__xnor3_1 _506_ (
    .A(_192_),
    .B(_218_),
    .C(_220_),
    .X(_247_)
  );
  sky130_fd_sc_hd__mux2_1 _507_ (
    .A0(\ra[7] ),
    .A1(a[7]),
    .S(en),
    .X(_051_)
  );
  sky130_fd_sc_hd__or2_0 _508_ (
    .A(acc[9]),
    .B(\p[9] ),
    .X(_071_)
  );
  sky130_fd_sc_hd__nand2_1 _509_ (
    .A(\ra[0] ),
    .B(\rb[5] ),
    .Y(_248_)
  );
  sky130_fd_sc_hd__nand2_1 _510_ (
    .A(\ra[1] ),
    .B(\rb[4] ),
    .Y(_249_)
  );
  sky130_fd_sc_hd__nand2_1 _511_ (
    .A(\ra[1] ),
    .B(\rb[3] ),
    .Y(_250_)
  );
  sky130_fd_sc_hd__xnor3_1 _512_ (
    .A(_225_),
    .B(_248_),
    .C(_249_),
    .X(_251_)
  );
  sky130_fd_sc_hd__maj3_1 _513_ (
    .A(_246_),
    .B(_247_),
    .C(_251_),
    .X(_252_)
  );
  sky130_fd_sc_hd__xnor3_1 _514_ (
    .A(_221_),
    .B(_222_),
    .C(_226_),
    .X(_253_)
  );
  sky130_fd_sc_hd__maj3_1 _515_ (
    .A(_225_),
    .B(_248_),
    .C(_249_),
    .X(_254_)
  );
  sky130_fd_sc_hd__nand2_1 _516_ (
    .A(\ra[0] ),
    .B(\rb[6] ),
    .Y(_255_)
  );
  sky130_fd_sc_hd__nor2_1 _517_ (
    .A(_254_),
    .B(_255_),
    .Y(_256_)
  );
  sky130_fd_sc_hd__xor2_1 _518_ (
    .A(_254_),
    .B(_255_),
    .X(_257_)
  );
  sky130_fd_sc_hd__nand2_1 _519_ (
    .A(acc[8]),
    .B(\p[8] ),
    .Y(_072_)
  );
  sky130_fd_sc_hd__xnor2_1 _520_ (
    .A(_252_),
    .B(_253_),
    .Y(_258_)
  );
  sky130_fd_sc_hd__maj3_1 _521_ (
    .A(_252_),
    .B(_253_),
    .C(_257_),
    .X(_259_)
  );
  sky130_fd_sc_hd__xor2_1 _522_ (
    .A(_232_),
    .B(_233_),
    .X(_260_)
  );
  sky130_fd_sc_hd__xor2_1 _523_ (
    .A(_259_),
    .B(_260_),
    .X(_261_)
  );
  sky130_fd_sc_hd__maj3_1 _524_ (
    .A(_256_),
    .B(_259_),
    .C(_260_),
    .X(_262_)
  );
  sky130_fd_sc_hd__xor2_1 _525_ (
    .A(_237_),
    .B(_238_),
    .X(_263_)
  );
  sky130_fd_sc_hd__nand2_1 _526_ (
    .A(_262_),
    .B(_263_),
    .Y(_264_)
  );
  sky130_fd_sc_hd__xnor2_1 _527_ (
    .A(_262_),
    .B(_263_),
    .Y(_265_)
  );
  sky130_fd_sc_hd__xnor2_1 _528_ (
    .A(_256_),
    .B(_261_),
    .Y(_266_)
  );
  sky130_fd_sc_hd__nand2_1 _529_ (
    .A(\ra[2] ),
    .B(\rb[1] ),
    .Y(_267_)
  );
  sky130_fd_sc_hd__nor2_1 _530_ (
    .A(acc[8]),
    .B(\p[8] ),
    .Y(_073_)
  );
  sky130_fd_sc_hd__nand2_1 _531_ (
    .A(\ra[2] ),
    .B(\rb[0] ),
    .Y(_268_)
  );
  sky130_fd_sc_hd__nand2_1 _532_ (
    .A(\ra[1] ),
    .B(\rb[2] ),
    .Y(_269_)
  );
  sky130_fd_sc_hd__xnor2_1 _533_ (
    .A(_244_),
    .B(_267_),
    .Y(_270_)
  );
  sky130_fd_sc_hd__maj3_1 _534_ (
    .A(_244_),
    .B(_267_),
    .C(_269_),
    .X(_271_)
  );
  sky130_fd_sc_hd__xnor3_1 _535_ (
    .A(_219_),
    .B(_243_),
    .C(_245_),
    .X(_272_)
  );
  sky130_fd_sc_hd__nand2_1 _536_ (
    .A(\ra[0] ),
    .B(\rb[4] ),
    .Y(_273_)
  );
  sky130_fd_sc_hd__nand2_1 _537_ (
    .A(\ra[0] ),
    .B(\rb[3] ),
    .Y(_274_)
  );
  sky130_fd_sc_hd__nor2_1 _538_ (
    .A(_250_),
    .B(_273_),
    .Y(_275_)
  );
  sky130_fd_sc_hd__xnor2_1 _539_ (
    .A(_250_),
    .B(_273_),
    .Y(_276_)
  );
  sky130_fd_sc_hd__maj3_1 _540_ (
    .A(_271_),
    .B(_272_),
    .C(_276_),
    .X(_277_)
  );
  sky130_fd_sc_hd__xor2_1 _541_ (
    .A(acc[8]),
    .B(\p[8] ),
    .X(_074_)
  );
  sky130_fd_sc_hd__clkinv_1 _542_ (
    .A(_277_),
    .Y(_278_)
  );
  sky130_fd_sc_hd__xor3_1 _543_ (
    .A(_246_),
    .B(_247_),
    .C(_251_),
    .X(_279_)
  );
  sky130_fd_sc_hd__xor2_1 _544_ (
    .A(_277_),
    .B(_279_),
    .X(_280_)
  );
  sky130_fd_sc_hd__maj3_1 _545_ (
    .A(_275_),
    .B(_278_),
    .C(_279_),
    .X(_281_)
  );
  sky130_fd_sc_hd__xnor2_1 _546_ (
    .A(_257_),
    .B(_258_),
    .Y(_282_)
  );
  sky130_fd_sc_hd__nand2_1 _547_ (
    .A(_281_),
    .B(_282_),
    .Y(_283_)
  );
  sky130_fd_sc_hd__xnor2_1 _548_ (
    .A(_281_),
    .B(_282_),
    .Y(_284_)
  );
  sky130_fd_sc_hd__nand2_1 _549_ (
    .A(\ra[1] ),
    .B(\rb[1] ),
    .Y(_285_)
  );
  sky130_fd_sc_hd__nand2_1 _550_ (
    .A(\ra[0] ),
    .B(\rb[2] ),
    .Y(_286_)
  );
  sky130_fd_sc_hd__xor2_1 _551_ (
    .A(_268_),
    .B(_285_),
    .X(_287_)
  );
  sky130_fd_sc_hd__and2_0 _552_ (
    .A(acc[7]),
    .B(\p[7] ),
    .X(_075_)
  );
  sky130_fd_sc_hd__maj3_1 _553_ (
    .A(_268_),
    .B(_285_),
    .C(_286_),
    .X(_288_)
  );
  sky130_fd_sc_hd__xnor2_1 _554_ (
    .A(_269_),
    .B(_270_),
    .Y(_289_)
  );
  sky130_fd_sc_hd__maj3_1 _555_ (
    .A(_274_),
    .B(_288_),
    .C(_289_),
    .X(_290_)
  );
  sky130_fd_sc_hd__xnor3_1 _556_ (
    .A(_271_),
    .B(_272_),
    .C(_276_),
    .X(_291_)
  );
  sky130_fd_sc_hd__nand2b_1 _557_ (
    .A_N(_290_),
    .B(_291_),
    .Y(_292_)
  );
  sky130_fd_sc_hd__xnor2_1 _558_ (
    .A(_275_),
    .B(_280_),
    .Y(_293_)
  );
  sky130_fd_sc_hd__nand2b_1 _559_ (
    .A_N(_292_),
    .B(_293_),
    .Y(_294_)
  );
  sky130_fd_sc_hd__nand2_1 _560_ (
    .A(\ra[0] ),
    .B(\rb[0] ),
    .Y(_295_)
  );
  sky130_fd_sc_hd__nand4_1 _561_ (
    .A(\ra[0] ),
    .B(\ra[1] ),
    .C(\rb[0] ),
    .D(\rb[1] ),
    .Y(_296_)
  );
  sky130_fd_sc_hd__xnor2_1 _562_ (
    .A(_286_),
    .B(_287_),
    .Y(_297_)
  );
  sky130_fd_sc_hd__nor2_1 _563_ (
    .A(acc[7]),
    .B(\p[7] ),
    .Y(_076_)
  );
  sky130_fd_sc_hd__nand2b_1 _564_ (
    .A_N(_296_),
    .B(_297_),
    .Y(_298_)
  );
  sky130_fd_sc_hd__xor3_1 _565_ (
    .A(_274_),
    .B(_288_),
    .C(_289_),
    .X(_299_)
  );
  sky130_fd_sc_hd__nor2_1 _566_ (
    .A(_298_),
    .B(_299_),
    .Y(_300_)
  );
  sky130_fd_sc_hd__nand2b_1 _567_ (
    .A_N(_291_),
    .B(_290_),
    .Y(_301_)
  );
  sky130_fd_sc_hd__and2_0 _568_ (
    .A(_292_),
    .B(_301_),
    .X(_302_)
  );
  sky130_fd_sc_hd__nand2_1 _569_ (
    .A(_300_),
    .B(_302_),
    .Y(_303_)
  );
  sky130_fd_sc_hd__xor2_1 _570_ (
    .A(_292_),
    .B(_293_),
    .X(_304_)
  );
  sky130_fd_sc_hd__nand4_1 _571_ (
    .A(_292_),
    .B(_293_),
    .C(_300_),
    .D(_301_),
    .Y(_305_)
  );
  sky130_fd_sc_hd__a21o_1 _572_ (
    .A1(_294_),
    .A2(_305_),
    .B1(_284_),
    .X(_306_)
  );
  sky130_fd_sc_hd__a21oi_1 _573_ (
    .A1(_283_),
    .A2(_306_),
    .B1(_266_),
    .Y(_307_)
  );
  sky130_fd_sc_hd__and2_0 _574_ (
    .A(acc[6]),
    .B(\p[6] ),
    .X(_077_)
  );
  sky130_fd_sc_hd__a211o_1 _575_ (
    .A1(_283_),
    .A2(_306_),
    .B1(_265_),
    .C1(_266_),
    .X(_308_)
  );
  sky130_fd_sc_hd__xor2_1 _576_ (
    .A(_240_),
    .B(_241_),
    .X(_309_)
  );
  sky130_fd_sc_hd__a21o_1 _577_ (
    .A1(_264_),
    .A2(_308_),
    .B1(_309_),
    .X(_310_)
  );
  sky130_fd_sc_hd__nand2_1 _578_ (
    .A(_242_),
    .B(_310_),
    .Y(_311_)
  );
  sky130_fd_sc_hd__xor2_1 _579_ (
    .A(_215_),
    .B(_216_),
    .X(_312_)
  );
  sky130_fd_sc_hd__a21boi_0 _580_ (
    .A1(_242_),
    .A2(_310_),
    .B1_N(_312_),
    .Y(_313_)
  );
  sky130_fd_sc_hd__xor2_1 _581_ (
    .A(_189_),
    .B(_190_),
    .X(_314_)
  );
  sky130_fd_sc_hd__o21a_1 _582_ (
    .A1(_217_),
    .A2(_313_),
    .B1(_314_),
    .X(_315_)
  );
  sky130_fd_sc_hd__nor3_1 _583_ (
    .A(_159_),
    .B(_162_),
    .C(_163_),
    .Y(_316_)
  );
  sky130_fd_sc_hd__nor2_1 _584_ (
    .A(_164_),
    .B(_316_),
    .Y(_317_)
  );
  sky130_fd_sc_hd__nand2_1 _585_ (
    .A(acc[1]),
    .B(\p[1] ),
    .Y(_078_)
  );
  sky130_fd_sc_hd__o21a_1 _586_ (
    .A1(_191_),
    .A2(_315_),
    .B1(_317_),
    .X(_318_)
  );
  sky130_fd_sc_hd__nand2_1 _587_ (
    .A(_137_),
    .B(_142_),
    .Y(_319_)
  );
  sky130_fd_sc_hd__nand2_1 _588_ (
    .A(_143_),
    .B(_319_),
    .Y(_320_)
  );
  sky130_fd_sc_hd__o21bai_1 _589_ (
    .A1(_164_),
    .A2(_318_),
    .B1_N(_320_),
    .Y(_321_)
  );
  sky130_fd_sc_hd__nand3_1 _590_ (
    .A(\ra[7] ),
    .B(\rb[7] ),
    .C(_127_),
    .Y(_322_)
  );
  sky130_fd_sc_hd__maj3_1 _591_ (
    .A(_133_),
    .B(_138_),
    .C(_140_),
    .X(_323_)
  );
  sky130_fd_sc_hd__xor2_1 _592_ (
    .A(_322_),
    .B(_323_),
    .X(_324_)
  );
  sky130_fd_sc_hd__a21o_1 _593_ (
    .A1(_143_),
    .A2(_321_),
    .B1(_324_),
    .X(_325_)
  );
  sky130_fd_sc_hd__o211ai_1 _594_ (
    .A1(_128_),
    .A2(_323_),
    .B1(\ra[7] ),
    .C1(\rb[7] ),
    .Y(_326_)
  );
  sky130_fd_sc_hd__a31oi_1 _595_ (
    .A1(en),
    .A2(_325_),
    .A3(_326_),
    .B1(_110_),
    .Y(_047_)
  );
  sky130_fd_sc_hd__nand2_1 _596_ (
    .A(acc[0]),
    .B(\p[0] ),
    .Y(_079_)
  );
  sky130_fd_sc_hd__mux2_1 _597_ (
    .A0(\rb[7] ),
    .A1(b[7]),
    .S(en),
    .X(_046_)
  );
  sky130_fd_sc_hd__mux2_1 _598_ (
    .A0(\ra[0] ),
    .A1(a[0]),
    .S(en),
    .X(_045_)
  );
  sky130_fd_sc_hd__mux2_1 _599_ (
    .A0(\ra[1] ),
    .A1(a[1]),
    .S(en),
    .X(_044_)
  );
  sky130_fd_sc_hd__mux2_1 _600_ (
    .A0(\ra[2] ),
    .A1(a[2]),
    .S(en),
    .X(_043_)
  );
  sky130_fd_sc_hd__mux2_1 _601_ (
    .A0(\ra[3] ),
    .A1(a[3]),
    .S(en),
    .X(_042_)
  );
  sky130_fd_sc_hd__mux2_1 _602_ (
    .A0(\ra[4] ),
    .A1(a[4]),
    .S(en),
    .X(_041_)
  );
  sky130_fd_sc_hd__mux2_1 _603_ (
    .A0(\ra[5] ),
    .A1(a[5]),
    .S(en),
    .X(_040_)
  );
  sky130_fd_sc_hd__mux2_1 _604_ (
    .A0(\ra[6] ),
    .A1(a[6]),
    .S(en),
    .X(_039_)
  );
  sky130_fd_sc_hd__xnor2_1 _605_ (
    .A(_062_),
    .B(_099_),
    .Y(_327_)
  );
  sky130_fd_sc_hd__nor2_1 _606_ (
    .A(en),
    .B(acc[12]),
    .Y(_328_)
  );
  sky130_fd_sc_hd__xnor2_1 _607_ (
    .A(acc[1]),
    .B(\p[1] ),
    .Y(_080_)
  );
  sky130_fd_sc_hd__a21oi_1 _608_ (
    .A1(en),
    .A2(_327_),
    .B1(_328_),
    .Y(_038_)
  );
  sky130_fd_sc_hd__xnor2_1 _609_ (
    .A(_069_),
    .B(_096_),
    .Y(_329_)
  );
  sky130_fd_sc_hd__nor2_1 _610_ (
    .A(en),
    .B(acc[10]),
    .Y(_330_)
  );
  sky130_fd_sc_hd__a21oi_1 _611_ (
    .A1(en),
    .A2(_329_),
    .B1(_330_),
    .Y(_037_)
  );
  sky130_fd_sc_hd__xnor2_1 _612_ (
    .A(_074_),
    .B(_094_),
    .Y(_331_)
  );
  sky130_fd_sc_hd__nor2_1 _613_ (
    .A(en),
    .B(acc[8]),
    .Y(_332_)
  );
  sky130_fd_sc_hd__a21oi_1 _614_ (
    .A1(en),
    .A2(_331_),
    .B1(_332_),
    .Y(_036_)
  );
  sky130_fd_sc_hd__xnor2_1 _615_ (
    .A(\p[15] ),
    .B(acc[15]),
    .Y(_333_)
  );
  sky130_fd_sc_hd__xnor2_1 _616_ (
    .A(_102_),
    .B(_333_),
    .Y(_334_)
  );
  sky130_fd_sc_hd__nor2_1 _617_ (
    .A(en),
    .B(acc[15]),
    .Y(_335_)
  );
  sky130_fd_sc_hd__nand2_1 _618_ (
    .A(\p[15] ),
    .B(acc[15]),
    .Y(_054_)
  );
  sky130_fd_sc_hd__o21ai_0 _619_ (
    .A1(_079_),
    .A2(_080_),
    .B1(_078_),
    .Y(_081_)
  );
  sky130_fd_sc_hd__a21oi_1 _620_ (
    .A1(en),
    .A2(_334_),
    .B1(_335_),
    .Y(_035_)
  );
  sky130_fd_sc_hd__xnor2_1 _621_ (
    .A(_089_),
    .B(_091_),
    .Y(_336_)
  );
  sky130_fd_sc_hd__nor2_1 _622_ (
    .A(en),
    .B(acc[6]),
    .Y(_337_)
  );
  sky130_fd_sc_hd__a21oi_1 _623_ (
    .A1(en),
    .A2(_336_),
    .B1(_337_),
    .Y(_034_)
  );
  sky130_fd_sc_hd__nor2_1 _624_ (
    .A(en),
    .B(acc[11]),
    .Y(_338_)
  );
  sky130_fd_sc_hd__nand2_1 _625_ (
    .A(_064_),
    .B(_066_),
    .Y(_339_)
  );
  sky130_fd_sc_hd__xnor2_1 _626_ (
    .A(_098_),
    .B(_339_),
    .Y(_340_)
  );
  sky130_fd_sc_hd__a21oi_1 _627_ (
    .A1(en),
    .A2(_340_),
    .B1(_338_),
    .Y(_033_)
  );
  sky130_fd_sc_hd__nor2b_1 _628_ (
    .A(en),
    .B_N(\p[14] ),
    .Y(_341_)
  );
  sky130_fd_sc_hd__nand3_1 _629_ (
    .A(_143_),
    .B(_321_),
    .C(_324_),
    .Y(_342_)
  );
  sky130_fd_sc_hd__xor2_1 _630_ (
    .A(acc[2]),
    .B(\p[2] ),
    .X(_082_)
  );
  sky130_fd_sc_hd__a31o_1 _631_ (
    .A1(en),
    .A2(_325_),
    .A3(_342_),
    .B1(_341_),
    .X(_032_)
  );
  sky130_fd_sc_hd__xnor2_1 _632_ (
    .A(_057_),
    .B(_101_),
    .Y(_343_)
  );
  sky130_fd_sc_hd__nor2_1 _633_ (
    .A(en),
    .B(acc[14]),
    .Y(_344_)
  );
  sky130_fd_sc_hd__a21oi_1 _634_ (
    .A1(en),
    .A2(_343_),
    .B1(_344_),
    .Y(_031_)
  );
  sky130_fd_sc_hd__nor2_1 _635_ (
    .A(acc[16]),
    .B(_104_),
    .Y(_345_)
  );
  sky130_fd_sc_hd__nor2_1 _636_ (
    .A(_105_),
    .B(_345_),
    .Y(_030_)
  );
  sky130_fd_sc_hd__xnor2_1 _637_ (
    .A(acc[13]),
    .B(\p[13] ),
    .Y(_346_)
  );
  sky130_fd_sc_hd__nand3_1 _638_ (
    .A(_060_),
    .B(_100_),
    .C(_346_),
    .Y(_347_)
  );
  sky130_fd_sc_hd__a21oi_1 _639_ (
    .A1(_060_),
    .A2(_100_),
    .B1(_346_),
    .Y(_348_)
  );
  sky130_fd_sc_hd__nor3b_1 _640_ (
    .A(_348_),
    .B(_052_),
    .C_N(_347_),
    .Y(_349_)
  );
  sky130_fd_sc_hd__maj3_1 _641_ (
    .A(acc[2]),
    .B(\p[2] ),
    .C(_081_),
    .X(_083_)
  );
  sky130_fd_sc_hd__a21o_1 _642_ (
    .A1(_052_),
    .A2(acc[13]),
    .B1(_349_),
    .X(_029_)
  );
  sky130_fd_sc_hd__xnor2_1 _643_ (
    .A(_079_),
    .B(_080_),
    .Y(_350_)
  );
  sky130_fd_sc_hd__nor2_1 _644_ (
    .A(en),
    .B(acc[1]),
    .Y(_351_)
  );
  sky130_fd_sc_hd__a21oi_1 _645_ (
    .A1(en),
    .A2(_350_),
    .B1(_351_),
    .Y(_028_)
  );
  sky130_fd_sc_hd__nor3b_1 _646_ (
    .A(_164_),
    .B(_318_),
    .C_N(_320_),
    .Y(_352_)
  );
  sky130_fd_sc_hd__nand2_1 _647_ (
    .A(en),
    .B(_321_),
    .Y(_353_)
  );
  sky130_fd_sc_hd__o2bb2ai_1 _648_ (
    .A1_N(_052_),
    .A2_N(\p[13] ),
    .B1(_352_),
    .B2(_353_),
    .Y(_027_)
  );
  sky130_fd_sc_hd__xnor2_1 _649_ (
    .A(_083_),
    .B(_084_),
    .Y(_354_)
  );
  sky130_fd_sc_hd__nor2_1 _650_ (
    .A(en),
    .B(acc[3]),
    .Y(_355_)
  );
  sky130_fd_sc_hd__a21oi_1 _651_ (
    .A1(en),
    .A2(_354_),
    .B1(_355_),
    .Y(_026_)
  );
  sky130_fd_sc_hd__xor2_1 _652_ (
    .A(acc[3]),
    .B(\p[3] ),
    .X(_084_)
  );
  sky130_fd_sc_hd__nand2_1 _653_ (
    .A(en),
    .B(\p[0] ),
    .Y(_356_)
  );
  sky130_fd_sc_hd__xnor2_1 _654_ (
    .A(acc[0]),
    .B(_356_),
    .Y(_025_)
  );
  sky130_fd_sc_hd__xnor2_1 _655_ (
    .A(_087_),
    .B(_088_),
    .Y(_357_)
  );
  sky130_fd_sc_hd__nor2_1 _656_ (
    .A(en),
    .B(acc[5]),
    .Y(_358_)
  );
  sky130_fd_sc_hd__a21oi_1 _657_ (
    .A1(en),
    .A2(_357_),
    .B1(_358_),
    .Y(_024_)
  );
  sky130_fd_sc_hd__nor3_1 _658_ (
    .A(_191_),
    .B(_315_),
    .C(_317_),
    .Y(_359_)
  );
  sky130_fd_sc_hd__nor3_1 _659_ (
    .A(_052_),
    .B(_318_),
    .C(_359_),
    .Y(_360_)
  );
  sky130_fd_sc_hd__a21o_1 _660_ (
    .A1(_052_),
    .A2(\p[12] ),
    .B1(_360_),
    .X(_023_)
  );
  sky130_fd_sc_hd__nor2_1 _661_ (
    .A(_075_),
    .B(_076_),
    .Y(_361_)
  );
  sky130_fd_sc_hd__xor2_1 _662_ (
    .A(_092_),
    .B(_361_),
    .X(_362_)
  );
  sky130_fd_sc_hd__maj3_1 _663_ (
    .A(acc[3]),
    .B(\p[3] ),
    .C(_083_),
    .X(_085_)
  );
  sky130_fd_sc_hd__mux2_1 _664_ (
    .A0(acc[7]),
    .A1(_362_),
    .S(en),
    .X(_022_)
  );
  sky130_fd_sc_hd__nor2b_1 _665_ (
    .A(_070_),
    .B_N(_071_),
    .Y(_363_)
  );
  sky130_fd_sc_hd__xnor2_1 _666_ (
    .A(_095_),
    .B(_363_),
    .Y(_364_)
  );
  sky130_fd_sc_hd__nor2_1 _667_ (
    .A(en),
    .B(acc[9]),
    .Y(_365_)
  );
  sky130_fd_sc_hd__a21oi_1 _668_ (
    .A1(en),
    .A2(_364_),
    .B1(_365_),
    .Y(_021_)
  );
  sky130_fd_sc_hd__xor2_1 _669_ (
    .A(acc[17]),
    .B(_105_),
    .X(_020_)
  );
  sky130_fd_sc_hd__xnor2_1 _670_ (
    .A(_081_),
    .B(_082_),
    .Y(_366_)
  );
  sky130_fd_sc_hd__nor2_1 _671_ (
    .A(en),
    .B(acc[2]),
    .Y(_367_)
  );
  sky130_fd_sc_hd__a21oi_1 _672_ (
    .A1(en),
    .A2(_366_),
    .B1(_367_),
    .Y(_019_)
  );
  sky130_fd_sc_hd__mux2_1 _673_ (
    .A0(\rb[0] ),
    .A1(b[0]),
    .S(en),
    .X(_018_)
  );
  sky130_fd_sc_hd__xor2_1 _674_ (
    .A(acc[4]),
    .B(\p[4] ),
    .X(_086_)
  );
  sky130_fd_sc_hd__mux2_1 _675_ (
    .A0(\rb[1] ),
    .A1(b[1]),
    .S(en),
    .X(_017_)
  );
  sky130_fd_sc_hd__mux2_1 _676_ (
    .A0(\rb[2] ),
    .A1(b[2]),
    .S(en),
    .X(_016_)
  );
  sky130_fd_sc_hd__mux2_1 _677_ (
    .A0(\rb[3] ),
    .A1(b[3]),
    .S(en),
    .X(_015_)
  );
  sky130_fd_sc_hd__mux2_1 _678_ (
    .A0(\rb[4] ),
    .A1(b[4]),
    .S(en),
    .X(_014_)
  );
  sky130_fd_sc_hd__mux2_1 _679_ (
    .A0(\rb[5] ),
    .A1(b[5]),
    .S(en),
    .X(_013_)
  );
  sky130_fd_sc_hd__mux2_1 _680_ (
    .A0(\rb[6] ),
    .A1(b[6]),
    .S(en),
    .X(_012_)
  );
  sky130_fd_sc_hd__nor2_1 _681_ (
    .A(en),
    .B(\p[0] ),
    .Y(_368_)
  );
  sky130_fd_sc_hd__a21oi_1 _682_ (
    .A1(en),
    .A2(_295_),
    .B1(_368_),
    .Y(_011_)
  );
  sky130_fd_sc_hd__a22oi_1 _683_ (
    .A1(\ra[1] ),
    .A2(\rb[0] ),
    .B1(\rb[1] ),
    .B2(\ra[0] ),
    .Y(_369_)
  );
  sky130_fd_sc_hd__nand2_1 _684_ (
    .A(en),
    .B(_296_),
    .Y(_370_)
  );
  sky130_fd_sc_hd__maj3_1 _685_ (
    .A(acc[4]),
    .B(\p[4] ),
    .C(_085_),
    .X(_087_)
  );
  sky130_fd_sc_hd__o2bb2ai_1 _686_ (
    .A1_N(_052_),
    .A2_N(\p[1] ),
    .B1(_369_),
    .B2(_370_),
    .Y(_010_)
  );
  sky130_fd_sc_hd__xor2_1 _687_ (
    .A(_296_),
    .B(_297_),
    .X(_371_)
  );
  sky130_fd_sc_hd__nor2_1 _688_ (
    .A(en),
    .B(\p[2] ),
    .Y(_372_)
  );
  sky130_fd_sc_hd__a21oi_1 _689_ (
    .A1(en),
    .A2(_371_),
    .B1(_372_),
    .Y(_009_)
  );
  sky130_fd_sc_hd__xnor2_1 _690_ (
    .A(_298_),
    .B(_299_),
    .Y(_373_)
  );
  sky130_fd_sc_hd__nor2_1 _691_ (
    .A(en),
    .B(\p[3] ),
    .Y(_374_)
  );
  sky130_fd_sc_hd__a21oi_1 _692_ (
    .A1(en),
    .A2(_373_),
    .B1(_374_),
    .Y(_008_)
  );
  sky130_fd_sc_hd__nor2_1 _693_ (
    .A(_300_),
    .B(_302_),
    .Y(_375_)
  );
  sky130_fd_sc_hd__nand2_1 _694_ (
    .A(en),
    .B(_303_),
    .Y(_376_)
  );
  sky130_fd_sc_hd__o2bb2ai_1 _695_ (
    .A1_N(_052_),
    .A2_N(\p[4] ),
    .B1(_375_),
    .B2(_376_),
    .Y(_007_)
  );
  sky130_fd_sc_hd__xor2_1 _696_ (
    .A(acc[5]),
    .B(\p[5] ),
    .X(_088_)
  );
  sky130_fd_sc_hd__nand2_1 _697_ (
    .A(_303_),
    .B(_304_),
    .Y(_377_)
  );
  sky130_fd_sc_hd__nand2_1 _698_ (
    .A(_305_),
    .B(_377_),
    .Y(_378_)
  );
  sky130_fd_sc_hd__nor2_1 _699_ (
    .A(en),
    .B(\p[5] ),
    .Y(_379_)
  );
  sky130_fd_sc_hd__a21oi_1 _700_ (
    .A1(en),
    .A2(_378_),
    .B1(_379_),
    .Y(_006_)
  );
  sky130_fd_sc_hd__nand3_1 _701_ (
    .A(_284_),
    .B(_294_),
    .C(_305_),
    .Y(_380_)
  );
  sky130_fd_sc_hd__a21oi_1 _702_ (
    .A1(_306_),
    .A2(_380_),
    .B1(_052_),
    .Y(_381_)
  );
  sky130_fd_sc_hd__nor2_1 _703_ (
    .A(en),
    .B(\p[6] ),
    .Y(_382_)
  );
  sky130_fd_sc_hd__nor2_1 _704_ (
    .A(_381_),
    .B(_382_),
    .Y(_005_)
  );
  sky130_fd_sc_hd__nor2_1 _705_ (
    .A(en),
    .B(\p[7] ),
    .Y(_383_)
  );
  sky130_fd_sc_hd__nand3_1 _706_ (
    .A(_266_),
    .B(_283_),
    .C(_306_),
    .Y(_384_)
  );
  sky130_fd_sc_hd__maj3_1 _707_ (
    .A(acc[5]),
    .B(\p[5] ),
    .C(_087_),
    .X(_089_)
  );
  sky130_fd_sc_hd__nand2b_1 _708_ (
    .A_N(_307_),
    .B(_384_),
    .Y(_385_)
  );
  sky130_fd_sc_hd__a21oi_1 _709_ (
    .A1(en),
    .A2(_385_),
    .B1(_383_),
    .Y(_004_)
  );
  sky130_fd_sc_hd__xor2_1 _710_ (
    .A(_265_),
    .B(_307_),
    .X(_386_)
  );
  sky130_fd_sc_hd__nor2_1 _711_ (
    .A(en),
    .B(\p[8] ),
    .Y(_387_)
  );
  sky130_fd_sc_hd__a21oi_1 _712_ (
    .A1(en),
    .A2(_386_),
    .B1(_387_),
    .Y(_003_)
  );
  sky130_fd_sc_hd__nand3_1 _713_ (
    .A(_264_),
    .B(_308_),
    .C(_309_),
    .Y(_388_)
  );
  sky130_fd_sc_hd__a21oi_1 _714_ (
    .A1(_310_),
    .A2(_388_),
    .B1(_052_),
    .Y(_389_)
  );
  sky130_fd_sc_hd__nor2_1 _715_ (
    .A(en),
    .B(\p[9] ),
    .Y(_390_)
  );
  sky130_fd_sc_hd__nor2_1 _716_ (
    .A(_389_),
    .B(_390_),
    .Y(_002_)
  );
  sky130_fd_sc_hd__xnor2_1 _717_ (
    .A(_311_),
    .B(_312_),
    .Y(_391_)
  );
  sky130_fd_sc_hd__nor2_1 _718_ (
    .A(acc[6]),
    .B(\p[6] ),
    .Y(_090_)
  );
  sky130_fd_sc_hd__nor2_1 _719_ (
    .A(en),
    .B(\p[10] ),
    .Y(_392_)
  );
  sky130_fd_sc_hd__a21oi_1 _720_ (
    .A1(en),
    .A2(_391_),
    .B1(_392_),
    .Y(_001_)
  );
  sky130_fd_sc_hd__nor3_1 _721_ (
    .A(_217_),
    .B(_313_),
    .C(_314_),
    .Y(_393_)
  );
  sky130_fd_sc_hd__nor3_1 _722_ (
    .A(_052_),
    .B(_315_),
    .C(_393_),
    .Y(_394_)
  );
  sky130_fd_sc_hd__a21o_1 _723_ (
    .A1(_052_),
    .A2(\p[11] ),
    .B1(_394_),
    .X(_000_)
  );
  sky130_fd_sc_hd__and2_0 _724_ (
    .A(\p[14] ),
    .B(acc[14]),
    .X(_055_)
  );
  sky130_fd_sc_hd__nor2_1 _725_ (
    .A(_077_),
    .B(_090_),
    .Y(_091_)
  );
  sky130_fd_sc_hd__a21o_1 _726_ (
    .A1(_089_),
    .A2(_091_),
    .B1(_077_),
    .X(_092_)
  );
  sky130_fd_sc_hd__a211oi_1 _727_ (
    .A1(_089_),
    .A2(_091_),
    .B1(_075_),
    .C1(_077_),
    .Y(_093_)
  );
  sky130_fd_sc_hd__nor2_1 _728_ (
    .A(_076_),
    .B(_093_),
    .Y(_094_)
  );
  sky130_fd_sc_hd__o31ai_1 _729_ (
    .A1(_073_),
    .A2(_076_),
    .A3(_093_),
    .B1(_072_),
    .Y(_095_)
  );
  sky130_fd_sc_hd__o21a_1 _730_ (
    .A1(_070_),
    .A2(_095_),
    .B1(_071_),
    .X(_096_)
  );
  sky130_fd_sc_hd__o211a_1 _731_ (
    .A1(_070_),
    .A2(_095_),
    .B1(_071_),
    .C1(_069_),
    .X(_097_)
  );
  sky130_fd_sc_hd__nor2_1 _732_ (
    .A(_067_),
    .B(_097_),
    .Y(_098_)
  );
  sky130_fd_sc_hd__a21oi_1 _733_ (
    .A1(_064_),
    .A2(_098_),
    .B1(_065_),
    .Y(_099_)
  );
  sky130_fd_sc_hd__o311ai_0 _734_ (
    .A1(_063_),
    .A2(_067_),
    .A3(_097_),
    .B1(_066_),
    .C1(_062_),
    .Y(_100_)
  );
  sky130_fd_sc_hd__nor2_1 _735_ (
    .A(\p[14] ),
    .B(acc[14]),
    .Y(_056_)
  );
  sky130_fd_sc_hd__a31oi_1 _736_ (
    .A1(_058_),
    .A2(_060_),
    .A3(_100_),
    .B1(_059_),
    .Y(_101_)
  );
  sky130_fd_sc_hd__a21oi_1 _737_ (
    .A1(_057_),
    .A2(_101_),
    .B1(_055_),
    .Y(_102_)
  );
  sky130_fd_sc_hd__o21ai_0 _738_ (
    .A1(\p[15] ),
    .A2(acc[15]),
    .B1(en),
    .Y(_103_)
  );
  sky130_fd_sc_hd__a21oi_1 _739_ (
    .A1(_054_),
    .A2(_102_),
    .B1(_103_),
    .Y(_104_)
  );
  sky130_fd_sc_hd__a211oi_1 _740_ (
    .A1(_054_),
    .A2(_102_),
    .B1(_103_),
    .C1(_053_),
    .Y(_105_)
  );
  sky130_fd_sc_hd__nand2_1 _741_ (
    .A(acc[17]),
    .B(_105_),
    .Y(_106_)
  );
  sky130_fd_sc_hd__nand3_1 _742_ (
    .A(acc[18]),
    .B(acc[17]),
    .C(_105_),
    .Y(_107_)
  );
  sky130_fd_sc_hd__xnor2_1 _743_ (
    .A(acc[18]),
    .B(_106_),
    .Y(_050_)
  );
  sky130_fd_sc_hd__xnor2_1 _744_ (
    .A(_085_),
    .B(_086_),
    .Y(_108_)
  );
  sky130_fd_sc_hd__nor2_1 _745_ (
    .A(en),
    .B(acc[4]),
    .Y(_109_)
  );
  sky130_fd_sc_hd__nor2_1 _746_ (
    .A(_055_),
    .B(_056_),
    .Y(_057_)
  );
  sky130_fd_sc_hd__a21oi_1 _747_ (
    .A1(en),
    .A2(_108_),
    .B1(_109_),
    .Y(_049_)
  );
  sky130_fd_sc_hd__xnor2_1 _748_ (
    .A(acc[19]),
    .B(_107_),
    .Y(_048_)
  );
  sky130_fd_sc_hd__nor2_1 _749_ (
    .A(en),
    .B(\p[15] ),
    .Y(_110_)
  );
  sky130_fd_sc_hd__nand2_1 _750_ (
    .A(\rb[7] ),
    .B(\ra[4] ),
    .Y(_111_)
  );
  sky130_fd_sc_hd__nand2_1 _751_ (
    .A(\ra[6] ),
    .B(\rb[3] ),
    .Y(_112_)
  );
  sky130_fd_sc_hd__nand2_1 _752_ (
    .A(\ra[6] ),
    .B(\rb[4] ),
    .Y(_113_)
  );
  sky130_fd_sc_hd__nand2_1 _753_ (
    .A(\ra[7] ),
    .B(\rb[3] ),
    .Y(_114_)
  );
  sky130_fd_sc_hd__nand2_1 _754_ (
    .A(\ra[5] ),
    .B(\rb[5] ),
    .Y(_115_)
  );
  sky130_fd_sc_hd__xnor2_1 _755_ (
    .A(_113_),
    .B(_114_),
    .Y(_116_)
  );
  sky130_fd_sc_hd__maj3_1 _756_ (
    .A(_113_),
    .B(_114_),
    .C(_115_),
    .X(_117_)
  );
  sky130_fd_sc_hd__nand2_1 _757_ (
    .A(acc[13]),
    .B(\p[13] ),
    .Y(_058_)
  );
  sky130_fd_sc_hd__nand2_1 _758_ (
    .A(\ra[5] ),
    .B(\rb[6] ),
    .Y(_118_)
  );
  sky130_fd_sc_hd__xnor2_1 _759_ (
    .A(_117_),
    .B(_118_),
    .Y(_119_)
  );
  sky130_fd_sc_hd__xnor2_1 _760_ (
    .A(_111_),
    .B(_119_),
    .Y(_120_)
  );
  sky130_fd_sc_hd__nand2_1 _761_ (
    .A(\ra[7] ),
    .B(\rb[5] ),
    .Y(_121_)
  );
  sky130_fd_sc_hd__nor2_1 _762_ (
    .A(_113_),
    .B(_121_),
    .Y(_122_)
  );
  sky130_fd_sc_hd__a22oi_1 _763_ (
    .A1(\ra[7] ),
    .A2(\rb[4] ),
    .B1(\rb[5] ),
    .B2(\ra[6] ),
    .Y(_123_)
  );
  sky130_fd_sc_hd__nor2_1 _764_ (
    .A(_122_),
    .B(_123_),
    .Y(_124_)
  );
  sky130_fd_sc_hd__nand2b_1 _765_ (
    .A_N(_120_),
    .B(_124_),
    .Y(_125_)
  );
  sky130_fd_sc_hd__nand2_1 _766_ (
    .A(\rb[7] ),
    .B(\ra[5] ),
    .Y(_126_)
  );
  sky130_fd_sc_hd__nand2_1 _767_ (
    .A(\ra[6] ),
    .B(\rb[6] ),
    .Y(_127_)
  );
  sky130_fd_sc_hd__nor2_1 _768_ (
    .A(acc[13]),
    .B(\p[13] ),
    .Y(_059_)
  );
  sky130_fd_sc_hd__clkinv_1 _769_ (
    .A(_127_),
    .Y(_128_)
  );
  sky130_fd_sc_hd__nor2_1 _770_ (
    .A(_122_),
    .B(_128_),
    .Y(_129_)
  );
  sky130_fd_sc_hd__nand2_1 _771_ (
    .A(\rb[6] ),
    .B(_122_),
    .Y(_130_)
  );
  sky130_fd_sc_hd__a21oi_1 _772_ (
    .A1(\rb[6] ),
    .A2(_122_),
    .B1(_129_),
    .Y(_131_)
  );
  sky130_fd_sc_hd__xnor2_1 _773_ (
    .A(_126_),
    .B(_131_),
    .Y(_132_)
  );
  sky130_fd_sc_hd__nor2b_1 _774_ (
    .A(_121_),
    .B_N(_132_),
    .Y(_133_)
  );
  sky130_fd_sc_hd__xor2_1 _775_ (
    .A(_121_),
    .B(_132_),
    .X(_134_)
  );
  sky130_fd_sc_hd__maj3_1 _776_ (
    .A(_111_),
    .B(_117_),
    .C(_118_),
    .X(_135_)
  );
  sky130_fd_sc_hd__xnor2_1 _777_ (
    .A(_125_),
    .B(_134_),
    .Y(_136_)
  );
  sky130_fd_sc_hd__maj3_1 _778_ (
    .A(_125_),
    .B(_134_),
    .C(_135_),
    .X(_137_)
  );
  sky130_fd_sc_hd__nand2_1 _779_ (
    .A(acc[12]),
    .B(\p[12] ),
    .Y(_060_)
  );
  sky130_fd_sc_hd__o21ai_0 _780_ (
    .A1(_126_),
    .A2(_129_),
    .B1(_130_),
    .Y(_138_)
  );
  sky130_fd_sc_hd__a22oi_1 _781_ (
    .A1(\rb[7] ),
    .A2(\ra[6] ),
    .B1(\rb[6] ),
    .B2(\ra[7] ),
    .Y(_139_)
  );
  sky130_fd_sc_hd__a31oi_1 _782_ (
    .A1(\ra[7] ),
    .A2(\rb[7] ),
    .A3(_128_),
    .B1(_139_),
    .Y(_140_)
  );
  sky130_fd_sc_hd__xnor2_1 _783_ (
    .A(_133_),
    .B(_140_),
    .Y(_141_)
  );
  sky130_fd_sc_hd__xor2_1 _784_ (
    .A(_138_),
    .B(_141_),
    .X(_142_)
  );
  sky130_fd_sc_hd__or2_0 _785_ (
    .A(_137_),
    .B(_142_),
    .X(_143_)
  );
  sky130_fd_sc_hd__nand2_1 _786_ (
    .A(\ra[6] ),
    .B(\rb[1] ),
    .Y(_144_)
  );
  sky130_fd_sc_hd__nand2_1 _787_ (
    .A(\ra[4] ),
    .B(\rb[5] ),
    .Y(_145_)
  );
  sky130_fd_sc_hd__nand2_1 _788_ (
    .A(\ra[5] ),
    .B(\rb[4] ),
    .Y(_146_)
  );
  sky130_fd_sc_hd__nand2_1 _789_ (
    .A(\ra[5] ),
    .B(\rb[3] ),
    .Y(_147_)
  );
  sky130_fd_sc_hd__dfrtp_1 _790_ (
    .CLK(clk),
    .D(_012_),
    .Q(\rb[6] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _791_ (
    .CLK(clk),
    .D(_046_),
    .Q(\rb[7] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _792_ (
    .CLK(clk),
    .D(_011_),
    .Q(\p[0] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _793_ (
    .CLK(clk),
    .D(_010_),
    .Q(\p[1] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _794_ (
    .CLK(clk),
    .D(_009_),
    .Q(\p[2] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _795_ (
    .CLK(clk),
    .D(_008_),
    .Q(\p[3] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _796_ (
    .CLK(clk),
    .D(_007_),
    .Q(\p[4] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _797_ (
    .CLK(clk),
    .D(_006_),
    .Q(\p[5] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _798_ (
    .CLK(clk),
    .D(_005_),
    .Q(\p[6] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _799_ (
    .CLK(clk),
    .D(_004_),
    .Q(\p[7] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _800_ (
    .CLK(clk),
    .D(_003_),
    .Q(\p[8] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _801_ (
    .CLK(clk),
    .D(_002_),
    .Q(\p[9] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _802_ (
    .CLK(clk),
    .D(_001_),
    .Q(\p[10] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _803_ (
    .CLK(clk),
    .D(_000_),
    .Q(\p[11] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _804_ (
    .CLK(clk),
    .D(_023_),
    .Q(\p[12] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _805_ (
    .CLK(clk),
    .D(_027_),
    .Q(\p[13] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _806_ (
    .CLK(clk),
    .D(_032_),
    .Q(\p[14] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _807_ (
    .CLK(clk),
    .D(_047_),
    .Q(\p[15] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _808_ (
    .CLK(clk),
    .D(_025_),
    .Q(acc[0]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _809_ (
    .CLK(clk),
    .D(_028_),
    .Q(acc[1]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _810_ (
    .CLK(clk),
    .D(_019_),
    .Q(acc[2]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _811_ (
    .CLK(clk),
    .D(_026_),
    .Q(acc[3]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _812_ (
    .CLK(clk),
    .D(_049_),
    .Q(acc[4]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _813_ (
    .CLK(clk),
    .D(_024_),
    .Q(acc[5]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _814_ (
    .CLK(clk),
    .D(_034_),
    .Q(acc[6]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _815_ (
    .CLK(clk),
    .D(_022_),
    .Q(acc[7]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _816_ (
    .CLK(clk),
    .D(_036_),
    .Q(acc[8]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _817_ (
    .CLK(clk),
    .D(_021_),
    .Q(acc[9]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _818_ (
    .CLK(clk),
    .D(_037_),
    .Q(acc[10]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _819_ (
    .CLK(clk),
    .D(_033_),
    .Q(acc[11]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _820_ (
    .CLK(clk),
    .D(_038_),
    .Q(acc[12]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _821_ (
    .CLK(clk),
    .D(_029_),
    .Q(acc[13]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _822_ (
    .CLK(clk),
    .D(_031_),
    .Q(acc[14]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _823_ (
    .CLK(clk),
    .D(_035_),
    .Q(acc[15]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _824_ (
    .CLK(clk),
    .D(_030_),
    .Q(acc[16]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _825_ (
    .CLK(clk),
    .D(_020_),
    .Q(acc[17]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _826_ (
    .CLK(clk),
    .D(_050_),
    .Q(acc[18]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _827_ (
    .CLK(clk),
    .D(_048_),
    .Q(acc[19]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _828_ (
    .CLK(clk),
    .D(_045_),
    .Q(\ra[0] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _829_ (
    .CLK(clk),
    .D(_044_),
    .Q(\ra[1] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _830_ (
    .CLK(clk),
    .D(_043_),
    .Q(\ra[2] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _831_ (
    .CLK(clk),
    .D(_042_),
    .Q(\ra[3] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _832_ (
    .CLK(clk),
    .D(_041_),
    .Q(\ra[4] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _833_ (
    .CLK(clk),
    .D(_040_),
    .Q(\ra[5] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _834_ (
    .CLK(clk),
    .D(_039_),
    .Q(\ra[6] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _835_ (
    .CLK(clk),
    .D(_051_),
    .Q(\ra[7] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _836_ (
    .CLK(clk),
    .D(_018_),
    .Q(\rb[0] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _837_ (
    .CLK(clk),
    .D(_017_),
    .Q(\rb[1] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _838_ (
    .CLK(clk),
    .D(_016_),
    .Q(\rb[2] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _839_ (
    .CLK(clk),
    .D(_015_),
    .Q(\rb[3] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _840_ (
    .CLK(clk),
    .D(_014_),
    .Q(\rb[4] ),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _841_ (
    .CLK(clk),
    .D(_013_),
    .Q(\rb[5] ),
    .RESET_B(rst_n)
  );
endmodule

Check yourself

Predict the outputThe MAC's acc[13] bit has a clock-to-Q of 0.4571 ns into a 10 fF load. With a 5 ns clock and an output delay of 3 ns, what slack does OpenSTA report on the path to acc[13], in ns?

create_clock -name clk -period 5 [get_ports clk]
set_clock_transition 0.1 [all_clocks]
set_output_delay 3 -clock clk [all_outputs]
set_load 0.01 [all_outputs]

Conceptset_output_delay -min 0.1 -clock clk [get_ports y]: the outside logic is longer than its flop's hold time. What does the hold check at y require?

y may change from 0.1 ns before the edge onNothing: a positive minimum delay is ignoredy must be valid 0.1 ns before the next edgey must not change until 0.1 ns after the edge

ConceptWhy does a port often need its input delay given against a virtual clock?

Every input delay needs a clock without a sourceIt names an outside clock the block itself does not useA virtual clock makes the tool skip that port's hold checksVirtual clocks are faster to analyse than port clocks

ConceptThe en path passed by 0.1294 ns without a driving cell and failed by 0.3830 ns with one. Why?

The driving cell moves the clock edge at the portThe driving cell adds its own setup time to the pathA real driver takes time to charge the port's fanoutset_driving_cell doubles the input delay by default

ConceptThe block runs on a 5 ns clock. Which line is a mistake unless a multicycle path is intended?

set_input_delay 1.5 -clock clk [get_ports a]set_output_delay -min -0.1 -clock clk [get_ports y]set_output_delay 2 -clock clk [all_outputs]set_input_delay 6 -clock clk [get_ports b]

Remember

set_input_delay is when a signal arrives after the edge; set_output_delay is how much of the cycle the outside still needs.
Max delays feed setup, min delays feed hold; a negative min output delay is the outside hold time.
A driving cell and a load give the ports realistic delay and slew; without them boundary paths look faster.
Unconstrained I/O is not timed at all, so a block can pass alone and fail in the chip.