ASIC Point

Skew, latency and insertion delay

Split a clock's latency into source and network parts, tell global skew from the local skew that enters a slack, read OpenSTA's sign for skew, and see what a slow clock edge does to a flop.

Lesson
L5.1
Time
30 min
Runs on
OpenROAD
Check
6 questions

A summary of this small block said its clock skew was 0.3155 ns, and the block lead planned a week of tree rebalancing. Yet its only two hold checks passed, and each saw less than 0.08 ns of skew. The big number compared two flops that never exchange data.

Timing pathHold from fc to fd, far from the clock rootBoth flops hang off the long branch: fc after four clkbuf_1 cells, fd after five.

fc → fdhold check, earliest arrival1 cell

  • Clock latency
  • Cell delay
  • Hold time
Hold from fc to fd, far from the clock root00.10.20.30.40.50.60.7time (ns)launch and capture clk ↑Data arrivesRequired afterclock 0.4529 nsclock 0.4529fc/CLK → fc/Q (dfxtp_1): 0.2969 ns1 dfxtp_1clock 0.5306 nshold −0.0300 nsslack +0.2493 ns · metarrival 0.7498required 0.5006Hold from fc to fd, far from the clock root00.20.40.6time (ns)launch and capture clk ↑Data arrivesRequired afterclock 0.4529 nsclock 0.4529fc/CLK → fc/Q (dfxtp_1): 0.2969 ns1 dfxtp_1clock 0.5306 nshold −0.0300 nsslack +0.2493 ns · metarrival 0.7498required 0.5006
  1. Launch latency

    The edge reaches fc 0.4529 ns after it enters the clk port.

  2. Capture latency

    It reaches fd one buffer later, at 0.5306 ns. That gap of 0.0777 ns is the skew this check sees.

  3. Met

    Hold slack 0.2493 ns. The 0.3155 ns figure never enters it.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.4529 ns. Capture: clk rise edge at 0.0000 ns, latency 0.5306 ns, library hold time −0.0300 ns.

Arrival 0.7498 ns, required 0.5006 ns, slack 0.2493 ns (met).

CellArcThroughEdgeDelay (ns)Time (ns)Slew (ns)
1fc/CLK → fc/Qdfxtp_1rise0.29690.74980.0329
fc/Q → fd/Dwire qcrise0.00000.74980.0329
The report
Startpoint: fc (rising edge-triggered flip-flop clocked by clk)
Endpoint: fd (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     3    0.0066    0.0393    0.1441    0.1441 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0393    0.0000    0.1441 ^ l1/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0022    0.0388    0.0736    0.2176 ^ l1/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl1 (net)
                    0.0388    0.0000    0.2176 ^ l2/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0022    0.0388    0.0734    0.2910 ^ l2/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl2 (net)
                    0.0388    0.0000    0.2910 ^ l3/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0022    0.0388    0.0734    0.3644 ^ l3/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl3 (net)
                    0.0388    0.0000    0.3644 ^ l4/A (sky130_fd_sc_hd__clkbuf_1)
     2    0.0041    0.0600    0.0886    0.4529 ^ l4/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cc (net)
                    0.0600    0.0000    0.4529 ^ fc/CLK (sky130_fd_sc_hd__dfxtp_1)
     1    0.0017    0.0329    0.2969    0.7498 ^ fc/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 qc (net)
                    0.0329    0.0000    0.7498 ^ fd/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.7498   data arrival time

                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     3    0.0066    0.0393    0.1441    0.1441 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0393    0.0000    0.1441 ^ l1/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0022    0.0388    0.0736    0.2176 ^ l1/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl1 (net)
                    0.0388    0.0000    0.2176 ^ l2/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0022    0.0388    0.0734    0.2910 ^ l2/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl2 (net)
                    0.0388    0.0000    0.2910 ^ l3/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0022    0.0388    0.0734    0.3644 ^ l3/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cl3 (net)
                    0.0388    0.0000    0.3644 ^ l4/A (sky130_fd_sc_hd__clkbuf_1)
     2    0.0041    0.0600    0.0886    0.4529 ^ l4/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cc (net)
                    0.0600    0.0000    0.4529 ^ l5/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0355    0.0776    0.5306 ^ l5/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cd (net)
                    0.0355    0.0000    0.5306 ^ fd/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    0.5306   clock reconvergence pessimism
                             -0.0300    0.5006   library hold time
                                        0.5006   data required time
-------------------------------------------------------------------------------------
                                        0.5006   data required time
                                       -0.7498   data arrival time
-------------------------------------------------------------------------------------
                                        0.2493   slack (MET)

OpenSTA 3.1.0 on the sky130 tt library, propagated 1 ns clock with a 0.1 ns slew at the port, no wires.

Latency is source plus network

The latency of a clock at a flop is the time from the clock's origin to that flop's clock pin, and it has two parts. Source latency runs from the real origin, such as a PLL or an oscillator off the chip, to the point where create_clock defines the clock. Network latency runs from there through the buffers and wires to the clock pin.

ctree3: four flops on three branchesArrows from the root are the clock; the two arrows between flops are the only data paths. Each flop shows its latency from the run.
ctree3: four flops on three branchesArrows from the root are the clock; the two arrows between flops are the only data paths. Each flop shows its latency from the run. component root (clkbuf_4) from the clk port component ba 1 × clkbuf_1 component bb1 → bb 2 × clkbuf_1 component l1 → l4 4 × clkbuf_1 component fa L = 0.2151 ns component fb L = 0.2885 ns component fc L = 0.4529 ns component l5 → fd L = 0.5306 ns clockclockclockCLKCLKCLKCLKdatadata
  1. Earliest and latest

    fa sees the edge first, at 0.2151 ns; fd sees it last, at 0.5306 ns. Their difference, 0.3155 ns, is the global skew.

  2. A pair that talks

    fa launches into fb. Their local skew is 0.2885 − 0.2151 = 0.0734 ns.

  3. The other pair

    fc launches into fd: 0.5306 − 0.4529 = 0.0777 ns.

Read the diagram as text
  • root (clkbuf_4): from the clk port
  • ba: 1 × clkbuf_1
  • bb1 → bb: 2 × clkbuf_1
  • l1 → l4: 4 × clkbuf_1
  • fa: L = 0.2151 ns
  • fb: L = 0.2885 ns
  • fc: L = 0.4529 ns
  • l5 → fd: L = 0.5306 ns
  • root (clkbuf_4) → ba: clock
  • root (clkbuf_4) → bb1 → bb: clock
  • root (clkbuf_4) → l1 → l4: clock
  • ba → fa: CLK
  • bb1 → bb → fb: CLK
  • l1 → l4 → fc: CLK
  • l1 → l4 → l5 → fd: CLK
  • fa → fb: data
  • fc → l5 → fd: data

No data path joins fa and fd, so their large difference never enters a check.

The insertion delay is the network latency that the clock tree adds; engineers use the two names for the same number. Here it ranges from the earliest flop to the latest, because the branches differ.

The SDC treats the two parts differently. set_clock_latency -source gives the source latency, and it stays in every analysis. Plain set_clock_latency gives an estimated network latency for an ideal clock, one with no tree yet. Lesson L2.6 showed that set_propagated_clock replaces that estimate with the real buffer delays.

Global skew and local skew

Skew compares the latencies of two clock pins. On this site it is always Lcapture − Llaunch, the convention of L2.4. Positive skew means the capture flop sees the edge later: setup gains that time and hold loses it.

MeasurePinsValueEnters a slack?
Global skewlatest − earliest: fd − fa0.3155 nsNo: fa and fd share no path
Local skew, fa → fbfb − fa0.0734 nsYes: setup and hold of fa → fb
Local skew, fc → fdfd − fc0.0777 nsYes: setup and hold of fc → fd

Latencies from the setup and hold paths of one OpenSTA run of ctree3.

Global skew is the latest arrival minus the earliest over every sink of a clock. Local skew belongs to one launch and capture pair joined by a timing path. Only local skew appears in a slack. A tree can have a large global skew and still meet timing, if flops that talk sit on similar branches.

Tools differ on the sign. OpenSTA's report_clock_skew names the worst pair, fc → fd, and prints -0.0776 ns. It computes launch latency minus capture latency, the opposite of this site's sign. It also subtracts before rounding, so its last digit can differ from 0.5306 − 0.4529. Check the sign of any skew report against the two latencies before you act on it.

report_clock_latency prints the other view: the earliest pin, fa/CLK at 0.2151 ns, the latest, fd/CLK at 0.5306 ns, and their difference as "skew". That line is the global skew.

One more buffer moves both checks

Add one clkbuf_1, named bx, in front of fb. Its latency grows from 0.2885 to 0.3618 ns, so the local skew of fa → fb grows by 0.0733 ns, while the launch side stays as it was.

Timing pathHold from fa to fb with one more capture bufferfb's clock now passes bb1, bb and bx.

fa → fbhold check, earliest arrival1 cell

  • Clock latency
  • Cell delay
  • Hold time
Hold from fa to fb with one more capture buffer00.050.10.150.20.250.30.350.40.450.5time (ns)launch and capture clk ↑Data arrivesRequired afterclock 0.2151 nsclock 0.2151fa/CLK → fa/Q (dfxtp_1): 0.2878 ns1 dfxtp_1clock 0.3618 nshold −0.0300 nsslack +0.1710 ns · metarrival 0.5029required 0.3318Hold from fa to fb with one more capture buffer00.10.20.30.40.5time (ns)launch and capture clk ↑Data arrivesRequired afterclock 0.2151 nsclock 0.2151fa/CLK → fa/Q (dfxtp_1): 0.2878 ns1 dfxtp_1clock 0.3618 nshold −0.0300 nsslack +0.1710 ns · metarrival 0.5029required 0.3318
  1. Same launch

    fa still launches at 0.2151 ns, and its clock-to-Q is 0.2878 ns.

  2. Later capture

    fb's edge comes at 0.3618 ns, and the old data must stay until then.

  3. Less hold margin

    Hold slack 0.1710 ns, down from 0.2444 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.2151 ns. Capture: clk rise edge at 0.0000 ns, latency 0.3618 ns, library hold time −0.0300 ns.

Arrival 0.5029 ns, required 0.3318 ns, slack 0.1710 ns (met).

CellArcThroughEdgeDelay (ns)Time (ns)Slew (ns)
1fa/CLK → fa/Qdfxtp_1rise0.28780.50290.0329
fa/Q → fb/Dwire qarise0.00000.50290.0329
The report
Startpoint: fa (rising edge-triggered flip-flop clocked by clk)
Endpoint: fb (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     3    0.0066    0.0393    0.1441    0.1441 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0393    0.0000    0.1441 ^ ba/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0710    0.2151 ^ ba/X (sky130_fd_sc_hd__clkbuf_1)
                                                 ca (net)
                    0.0353    0.0000    0.2151 ^ fa/CLK (sky130_fd_sc_hd__dfxtp_1)
     1    0.0017    0.0329    0.2878    0.5029 ^ fa/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 qa (net)
                    0.0329    0.0000    0.5029 ^ fb/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.5029   data arrival time

                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     3    0.0066    0.0393    0.1441    0.1441 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0393    0.0000    0.1441 ^ bb1/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0022    0.0388    0.0736    0.2176 ^ bb1/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cb1 (net)
                    0.0388    0.0000    0.2176 ^ bb/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0022    0.0388    0.0734    0.2910 ^ bb/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cb2 (net)
                    0.0388    0.0000    0.2910 ^ bx/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0708    0.3618 ^ bx/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cb (net)
                    0.0353    0.0000    0.3618 ^ fb/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    0.3618   clock reconvergence pessimism
                             -0.0300    0.3318   library hold time
                                        0.3318   data required time
-------------------------------------------------------------------------------------
                                        0.3318   data required time
                                       -0.5029   data arrival time
-------------------------------------------------------------------------------------
                                        0.1710   slack (MET)

OpenSTA 3.1.0, the same SDC; the netlist has one more clkbuf_1.

fa → fbTwo capture buffersThree capture buffersChange
Capture latency0.2885 ns0.3618 ns0.0733 ns
Setup slack0.6889 ns0.7623 ns+0.0734 ns
Hold slack0.2444 ns0.1710 ns-0.0734 ns

Setup and hold paths of the two runs, 1 ns clock.

The four paths behind the table
Timing pathHold from fa to fb, two capture buffers

fa → fbhold check, earliest arrival1 cell

  • Clock latency
  • Cell delay
  • Hold time
Hold from fa to fb, two capture buffers00.050.10.150.20.250.30.350.40.450.5time (ns)launch and capture clk ↑Data arrivesRequired afterclock 0.2151 nsclock 0.2151fa/CLK → fa/Q (dfxtp_1): 0.2878 ns1 dfxtp_1clock 0.2885 nshold −0.0300 nsslack +0.2444 ns · metarrival 0.5029required 0.2584Hold from fa to fb, two capture buffers00.10.20.30.40.5time (ns)launch and capture clk ↑Data arrivesRequired afterclock 0.2151 nsclock 0.2151fa/CLK → fa/Q (dfxtp_1): 0.2878 ns1 dfxtp_1clock 0.2885 nshold −0.0300 nsslack +0.2444 ns · metarrival 0.5029required 0.2584
Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.2151 ns. Capture: clk rise edge at 0.0000 ns, latency 0.2885 ns, library hold time −0.0300 ns.

Arrival 0.5029 ns, required 0.2584 ns, slack 0.2444 ns (met).

CellArcThroughEdgeDelay (ns)Time (ns)Slew (ns)
1fa/CLK → fa/Qdfxtp_1rise0.28780.50290.0329
fa/Q → fb/Dwire qarise0.00000.50290.0329
The report
Startpoint: fa (rising edge-triggered flip-flop clocked by clk)
Endpoint: fb (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     3    0.0066    0.0393    0.1441    0.1441 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0393    0.0000    0.1441 ^ ba/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0710    0.2151 ^ ba/X (sky130_fd_sc_hd__clkbuf_1)
                                                 ca (net)
                    0.0353    0.0000    0.2151 ^ fa/CLK (sky130_fd_sc_hd__dfxtp_1)
     1    0.0017    0.0329    0.2878    0.5029 ^ fa/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 qa (net)
                    0.0329    0.0000    0.5029 ^ fb/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.5029   data arrival time

                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     3    0.0066    0.0393    0.1441    0.1441 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0393    0.0000    0.1441 ^ bb1/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0022    0.0388    0.0736    0.2176 ^ bb1/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cb1 (net)
                    0.0388    0.0000    0.2176 ^ bb/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0708    0.2885 ^ bb/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cb (net)
                    0.0353    0.0000    0.2885 ^ fb/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    0.2885   clock reconvergence pessimism
                             -0.0300    0.2584   library hold time
                                        0.2584   data required time
-------------------------------------------------------------------------------------
                                        0.2584   data required time
                                       -0.5029   data arrival time
-------------------------------------------------------------------------------------
                                        0.2444   slack (MET)

The original tree, min path to fb.

Timing pathSetup from fa to fb, two capture buffers

fa → fbsetup check, latest arrival1 cell

  • Clock latency
  • Cell delay
  • Setup time
Setup from fa to fb, two capture buffers00.20.40.60.811.2time (ns)launch clk ↑capture clk ↑Data arrivesRequired byclock 0.2151 nsclock 0.2151fa/CLK → fa/Q (dfxtp_1): 0.2815 ns1 dfxtp_1clock 0.2885 nssetup −0.1029 nsslack +0.6889 ns · metarrival 0.4966required 1.1855Setup from fa to fb, two capture buffers00.51time (ns)launch clk ↑capture clk ↑Data arrivesRequired byclock 0.2151 nsfa/CLK → fa/Q (dfxtp_1): 0.2815 ns1 dfxtp_1clock 0.2885 nssetup −0.1029 nsslack +0.6889 ns · metarrival 0.4966required 1.1855
Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.2151 ns. Capture: clk rise edge at 1.0000 ns, latency 0.2885 ns, library setup time −0.1029 ns.

Arrival 0.4966 ns, required 1.1855 ns, slack 0.6889 ns (met).

CellArcThroughEdgeDelay (ns)Time (ns)Slew (ns)
1fa/CLK → fa/Qdfxtp_1fall0.28150.49660.0226
fa/Q → fb/Dwire qafall0.00000.49660.0226
The report
Startpoint: fa (rising edge-triggered flip-flop clocked by clk)
Endpoint: fb (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     3    0.0066    0.0393    0.1441    0.1441 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0393    0.0000    0.1441 ^ ba/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0710    0.2151 ^ ba/X (sky130_fd_sc_hd__clkbuf_1)
                                                 ca (net)
                    0.0353    0.0000    0.2151 ^ fa/CLK (sky130_fd_sc_hd__dfxtp_1)
     1    0.0017    0.0226    0.2815    0.4966 v fa/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 qa (net)
                    0.0226    0.0000    0.4966 v fb/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.4966   data arrival time

                              1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock source latency
     1    0.0022    0.1000    0.0000    1.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     3    0.0066    0.0393    0.1441    1.1441 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0393    0.0000    1.1441 ^ bb1/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0022    0.0388    0.0736    1.2176 ^ bb1/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cb1 (net)
                    0.0388    0.0000    1.2176 ^ bb/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0708    1.2885 ^ bb/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cb (net)
                    0.0353    0.0000    1.2885 ^ fb/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    1.2885   clock reconvergence pessimism
                             -0.1029    1.1855   library setup time
                                        1.1855   data required time
-------------------------------------------------------------------------------------
                                        1.1855   data required time
                                       -0.4966   data arrival time
-------------------------------------------------------------------------------------
                                        0.6889   slack (MET)

The original tree, max path to fb.

Timing pathSetup from fa to fb, three capture buffers

fa → fbsetup check, latest arrival1 cell

  • Clock latency
  • Cell delay
  • Setup time
Setup from fa to fb, three capture buffers00.20.40.60.811.21.4time (ns)launch clk ↑capture clk ↑Data arrivesRequired byclock 0.2151 nsclock 0.2151fa/CLK → fa/Q (dfxtp_1): 0.2815 ns1 dfxtp_1clock 0.3618 nssetup −0.1029 nsslack +0.7623 ns · metarrival 0.4966required 1.2589Setup from fa to fb, three capture buffers00.51time (ns)launch clk ↑capture clk ↑Data arrivesRequired byclock 0.2151 nsfa/CLK → fa/Q (dfxtp_1): 0.2815 ns1clock 0.3618 nssetup −0.1029 nsslack +0.7623 ns · metarrival 0.4966required 1.2589
Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.2151 ns. Capture: clk rise edge at 1.0000 ns, latency 0.3618 ns, library setup time −0.1029 ns.

Arrival 0.4966 ns, required 1.2589 ns, slack 0.7623 ns (met).

CellArcThroughEdgeDelay (ns)Time (ns)Slew (ns)
1fa/CLK → fa/Qdfxtp_1fall0.28150.49660.0226
fa/Q → fb/Dwire qafall0.00000.49660.0226
The report
Startpoint: fa (rising edge-triggered flip-flop clocked by clk)
Endpoint: fb (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     3    0.0066    0.0393    0.1441    0.1441 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0393    0.0000    0.1441 ^ ba/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0710    0.2151 ^ ba/X (sky130_fd_sc_hd__clkbuf_1)
                                                 ca (net)
                    0.0353    0.0000    0.2151 ^ fa/CLK (sky130_fd_sc_hd__dfxtp_1)
     1    0.0017    0.0226    0.2815    0.4966 v fa/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 qa (net)
                    0.0226    0.0000    0.4966 v fb/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.4966   data arrival time

                              1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock source latency
     1    0.0022    0.1000    0.0000    1.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     3    0.0066    0.0393    0.1441    1.1441 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0393    0.0000    1.1441 ^ bb1/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0022    0.0388    0.0736    1.2176 ^ bb1/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cb1 (net)
                    0.0388    0.0000    1.2176 ^ bb/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0022    0.0388    0.0734    1.2910 ^ bb/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cb2 (net)
                    0.0388    0.0000    1.2910 ^ bx/A (sky130_fd_sc_hd__clkbuf_1)
     1    0.0019    0.0353    0.0708    1.3618 ^ bx/X (sky130_fd_sc_hd__clkbuf_1)
                                                 cb (net)
                    0.0353    0.0000    1.3618 ^ fb/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    1.3618   clock reconvergence pessimism
                             -0.1029    1.2589   library setup time
                                        1.2589   data required time
-------------------------------------------------------------------------------------
                                        1.2589   data required time
                                       -0.4966   data arrival time
-------------------------------------------------------------------------------------
                                        0.7623   slack (MET)

With bx, max path to fb.

Setup gained what hold lost, to the last digit, and that trade is the subject of the next lessons. Useful skew moves a capture edge later on purpose to rescue a setup path, and the first thing it can break is the hold check of the same pair.

Jitter, uncertainty and a slow clock edge

Jitter is the variation of the clock source itself: one edge comes a little early, the next a little late. Ordinary CTS does not remove source jitter, and supply noise in the distribution network can add more. Clock uncertainty, set with set_clock_uncertainty, is the margin that covers it. Before the tree exists, the uncertainty also covers the skew still to come; after it, the real skew is in the latencies.

The tree has a second job besides balanced latencies: clean edges. The slew of a clock edge is its transition time, and a slow edge does more than arrive late, because the flop's own tables are indexed by it.

dfxtp_1, D rising, 0.01 ns data slewClock slew 0.01 nsClock slew 1.5 ns
setup time0.0508 ns-0.0454 ns
hold time-0.0285 ns0.0579 ns
clock-to-Q, Q rising, 0.5 fF load0.2692 ns0.5228 ns

The setup_rising, hold_rising and CLK → Q cell_rise tables of the pinned Liberty, first and last row.

With a slow clock edge, setup drops from 0.0508 to -0.0454 ns and hold rises from -0.0285 to 0.0579 ns. The window in which D must hold still moves later. Hold gets harder, and clock-to-Q grows by 0.2536 ns. That is why clock trees keep their edges sharp.

Asked in interviews

  1. Define clock skew and give its sign.

    The difference in clock arrival between the capture and the launch flop of a path, L_capture − L_launch. Positive skew gives setup time and takes the same time from hold. Some tools print launch − capture, so check the sign.

  2. What is the difference between global and local skew?

    Global skew is the latest minus the earliest clock arrival over all sinks. Local skew belongs to a pair of flops with a timing path between them, and only local skew enters a slack.

  3. What is insertion delay and why keep it small?

    The network latency the clock tree adds from the clock definition point to the flops. A long tree has more delay that can vary, and it shifts I/O paths against the outside world.

  4. What does clock uncertainty cover before and after CTS?

    Before CTS it covers jitter plus an estimate of the skew to come. After CTS the real skew is in the propagated latencies, so remove only the component already represented by propagated skew; retain justified jitter, variation and residual margins.

Try it

This is ctree3 from the figures. Run it and open Paths: the worst hold slack is 0.2444 ns, on fa → fb. Write down the launch and capture latency of each path and compute both local skews and the global skew.

Then add bx in the netlist tab: declare cb2, connect bb to cb2, and add sky130_fd_sc_hd__clkbuf_1 bx (.A(cb2), .X(cb));. Predict both slacks of fa → fb before you run. Finally add set_clock_latency -source 0.5 [get_clocks clk] to the SDC and see which numbers move.

STAOpenSTA in OpenROAD 26Q2 · sky130hd tt_025C_1v80 Liberty · simulator service
Edit the constraints or the netlist, then run

          

        
Expected: worst minimum slack 0.2444 ns clock skew -0.0776 ns latencyMin 0.2151 latencyMax 0.5306

        
        
        
      

    
Check yourself

      

        
Predict the outputBack to the original ctree3. The SDC gains set_clock_latency -source 0.5. What worst hold slack (WHS) does OpenSTA report, in ns?
      
create_clock -name clk -period 1.0 [get_ports clk]
set_propagated_clock [all_clocks]
set_input_transition 0.1 [get_ports clk]
set_clock_latency -source 0.5 [get_clocks clk]

Read the netlist: design.v
module ctree3 (clk, d, qb, qd);
  input clk;
  input d;
  output qb;
  output qd;
  wire cr, ca, cb1, cb, cl1, cl2, cl3, cc, cd, qa, qc;
  sky130_fd_sc_hd__clkbuf_4 root (.A(clk), .X(cr));
  sky130_fd_sc_hd__clkbuf_1 ba (.A(cr), .X(ca));
  sky130_fd_sc_hd__clkbuf_1 bb1 (.A(cr), .X(cb1));
  sky130_fd_sc_hd__clkbuf_1 bb (.A(cb1), .X(cb));
  sky130_fd_sc_hd__clkbuf_1 l1 (.A(cr), .X(cl1));
  sky130_fd_sc_hd__clkbuf_1 l2 (.A(cl1), .X(cl2));
  sky130_fd_sc_hd__clkbuf_1 l3 (.A(cl2), .X(cl3));
  sky130_fd_sc_hd__clkbuf_1 l4 (.A(cl3), .X(cc));
  sky130_fd_sc_hd__clkbuf_1 l5 (.A(cc), .X(cd));
  sky130_fd_sc_hd__dfxtp_1 fa (.CLK(ca), .D(d), .Q(qa));
  sky130_fd_sc_hd__dfxtp_1 fb (.CLK(cb), .D(qa), .Q(qb));
  sky130_fd_sc_hd__dfxtp_1 fc (.CLK(cc), .D(d), .Q(qc));
  sky130_fd_sc_hd__dfxtp_1 fd (.CLK(cd), .D(qc), .Q(qd));
endmodule


      

      

      


ConceptIn ctree3, report_clock_latency prints a skew of 0.3155 ns. Which number enters the hold check of fa → fb?


Conceptreport_clock_skew -hold prints -0.0776 ns for fc → fd. On this site's sign, Lcapture − Llaunch, what is that pair's skew and which check does it hurt?


ConceptA tree delivers a 1.5 ns clock edge to a dfxtp_1 instead of a 0.01 ns one. What happens to the flop's setup and hold times for a rising D?


ConceptWhich of these can clock tree synthesis reduce?


ConceptBefore CTS, an engineer expects the tree to add about 0.3 ns and writes the SDC below. Which line is the mistake?

        

        
      

    

    
Remember
  • Latency is source latency (before the clock definition) plus network latency (the tree); insertion delay is the network part.
  • Skew here is L_capture − L_launch; positive skew helps setup and hurts hold by the same amount.
  • Only local skew, between flops joined by a path, enters a slack; global skew compares any two sinks.
  • OpenSTA's report_clock_skew prints launch − capture, the opposite sign; check it against the latencies.
  • A slow clock edge raises clock-to-Q and moves the flop's setup and hold window later.