Useful skew: borrowing time between stages

Delay one register's clock on purpose to lend time from a short stage to a long one, and know the three limits: hold, loops and the cells that build the delay.

Lesson: L5.4
Time: 30 min
Runs on: OpenROAD
Check: 5 questions

A three-register pipeline missed a 1.25 ns clock by 0.3415 ns in its first stage. The stage after the middle register had 0.6964 ns to spare. Cutting the long stage again would add a cycle of latency.

Timing pathStage A misses the clockFlop a0 launches, the middle register r1 captures; six xor2_1 cells sit between them. The clock is ideal: every flop sees the edge at 0 ns.

a1 → r1setup check, latest arrival7 cells

Clock latency
Cell delay
Setup time

A long stage
Clock-to-Q and six XOR gates: the data arrives at 1.4819 ns.
The next edge
r1 samples at 1.25 ns, less its setup time: required at 1.1404 ns.
Violated
The data comes too late for this edge, and the slack is -0.3415 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 1.2500 ns, latency 0.0000 ns, library setup time −0.1096 ns.

Arrival 1.4819 ns, required 1.1404 ns, slack −0.3415 ns (violated).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`a1/CLK` → `a1/Q`	dfxtp_1	rise	0.4872	0.4872	0.2741
	`a1/Q` → `m1/B`	wire qa1	rise	0.0000	0.4872	0.2741
2	`m1/B` → `m1/X`	xor2_1	fall	0.1173	0.6045	0.0897
	`m1/X` → `m2/A`	wire s1	fall	0.0000	0.6045	0.0897
3	`m2/A` → `m2/X`	xor2_1	fall	0.1781	0.7827	0.0897
	`m2/X` → `m3/A`	wire s2	fall	0.0000	0.7827	0.0897
4	`m3/A` → `m3/X`	xor2_1	fall	0.1781	0.9608	0.0897
	`m3/X` → `m4/A`	wire s3	fall	0.0000	0.9608	0.0897
5	`m4/A` → `m4/X`	xor2_1	fall	0.1781	1.1389	0.0897
	`m4/X` → `m5/A`	wire s4	fall	0.0000	1.1389	0.0897
6	`m5/A` → `m5/X`	xor2_1	fall	0.1781	1.3170	0.0897
	`m5/X` → `m6/A`	wire s5	fall	0.0000	1.3170	0.0897
7	`m6/A` → `m6/X`	xor2_1	fall	0.1649	1.4819	0.0723
	`m6/X` → `r1/D`	wire s6	fall	0.0000	1.4819	0.0723

The report

Startpoint: a1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
Path Group: stageA
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                    0.1000    0.0000    0.0000 ^ a1/CLK (sky130_fd_sc_hd__dfxtp_1)
     7    0.0286    0.2741    0.4872    0.4872 ^ a1/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 qa1 (net)
                    0.2741    0.0000    0.4872 ^ m1/B (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1173    0.6045 v m1/X (sky130_fd_sc_hd__xor2_1)
                                                 s1 (net)
                    0.0897    0.0000    0.6045 v m2/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    0.7827 v m2/X (sky130_fd_sc_hd__xor2_1)
                                                 s2 (net)
                    0.0897    0.0000    0.7827 v m3/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    0.9608 v m3/X (sky130_fd_sc_hd__xor2_1)
                                                 s3 (net)
                    0.0897    0.0000    0.9608 v m4/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    1.1389 v m4/X (sky130_fd_sc_hd__xor2_1)
                                                 s4 (net)
                    0.0897    0.0000    1.1389 v m5/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    1.3170 v m5/X (sky130_fd_sc_hd__xor2_1)
                                                 s5 (net)
                    0.0897    0.0000    1.3170 v m6/A (sky130_fd_sc_hd__xor2_1)
     1    0.0017    0.0723    0.1649    1.4819 v m6/X (sky130_fd_sc_hd__xor2_1)
                                                 s6 (net)
                    0.0723    0.0000    1.4819 v r1/D (sky130_fd_sc_hd__dfxtp_1)
                                        1.4819   data arrival time

                    0.1000    1.2500    1.2500   clock clk (rise edge)
                              0.0000    1.2500   clock network delay (ideal)
                              0.0000    1.2500   clock reconvergence pessimism
                                        1.2500 ^ r1/CLK (sky130_fd_sc_hd__dfxtp_1)
                             -0.1096    1.1404   library setup time
                                        1.1404   data required time
-------------------------------------------------------------------------------------
                                        1.1404   data required time
                                       -1.4819   data arrival time
-------------------------------------------------------------------------------------
                                       -0.3415   slack (VIOLATED)

OpenSTA 3.1.0, sky130_fd_sc_hd tt library, ideal clock with a 0.1 ns clock slew, no wires.

The fix that worked moved no logic and added no flop, only a clock edge.

A late clock lends time

Call the middle register R: stage A ends at R and stage B starts there. Now delay R's clock by a latency L. For stage A, R is the capture flop, so its skew L_capture − L_launch is +L and its setup slack gains L. For stage B, R is the launch flop, so its skew is −L and its setup slack loses L. Time moves from stage B to stage A. Using skew this way is called useful skew, or clock skew scheduling.

The plot is one OpenSTA run of seven copies of the pipeline. Each copy gives R a different ideal latency with a pin-level set_clock_latency. The two setup slacks move in opposite directions by exactly L.

Measured sweepThree checks against the middle register's clock latencyA 1.25 ns ideal clock. Stage A ends at R, stage B starts at R, and "hold into R" is the shortest path into R: one and2_1.

stage A setup
stage B setup
hold into R

Latency of R 0 sstage A setup = -341.5 ps · stage B setup = 696.4 ps · hold into R = 474.2 ps
No skew: stage A -0.3415 ns, stage B 0.6964 ns, hold into R 0.4742 ns.
Latency of R 400 psstage A setup = 58.5 ps · stage B setup = 296.4 ps · hold into R = 74.2 ps
0.4 ns: stage A 0.0585 ns, stage B 0.2964 ns, hold 0.0742 ns. Every check passes.
Latency of R 500 psstage A setup = 158.5 ps · stage B setup = 196.4 ps · hold into R = -25.8 ps
0.5 ns: hold into R is -0.0258 ns. The late edge now catches the next value on the short path.

Read the plot as a table

Latency of R	stage A setup	stage B setup	hold into R
0 s	-341.5 ps	696.4 ps	474.2 ps
100 ps	-241.5 ps	596.4 ps	374.2 ps
200 ps	-141.5 ps	496.4 ps	274.2 ps
300 ps	-41.5 ps	396.4 ps	174.2 ps
400 ps	58.5 ps	296.4 ps	74.2 ps
400 ps	58.5 ps	296.4 ps	74.2 ps
500 ps	158.5 ps	196.4 ps	-25.8 ps
600 ps	258.5 ps	96.4 ps	-125.8 ps

OpenSTA 3.1.0, dfxtp_1, xor2_1 and and2_1 from the sky130_fd_sc_hd tt library, no wires.

The first limit is hold, on the stage that gains. Delaying R makes R hold its old value longer, so the shortest path into R must arrive later. Here hold fails above 0.4742 ns of latency, and stage A needs at least 0.3415 ns. The window between them is only 0.1327 ns wide. A wider one costs delay on the short path, which is hold repair (L5.5).

Stage A with R's clock 0.4 ns late

Timing pathStage A with a late capture edge

a1 → r1setup check, latest arrival7 cells

Clock latency
Cell delay
Setup time

Capture latency
R's edge comes 0.4000 ns late, and the required time moves with it.
Met
The same data now meets setup with a slack of 0.0585 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 1.2500 ns, latency 0.4000 ns, library setup time −0.1096 ns.

Arrival 1.4819 ns, required 1.5404 ns, slack 0.0585 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`a1/CLK` → `a1/Q`	dfxtp_1	rise	0.4872	0.4872	0.2741
	`a1/Q` → `m1/B`	wire qa1	rise	0.0000	0.4872	0.2741
2	`m1/B` → `m1/X`	xor2_1	fall	0.1173	0.6045	0.0897
	`m1/X` → `m2/A`	wire s1	fall	0.0000	0.6045	0.0897
3	`m2/A` → `m2/X`	xor2_1	fall	0.1781	0.7827	0.0897
	`m2/X` → `m3/A`	wire s2	fall	0.0000	0.7827	0.0897
4	`m3/A` → `m3/X`	xor2_1	fall	0.1781	0.9608	0.0897
	`m3/X` → `m4/A`	wire s3	fall	0.0000	0.9608	0.0897
5	`m4/A` → `m4/X`	xor2_1	fall	0.1781	1.1389	0.0897
	`m4/X` → `m5/A`	wire s4	fall	0.0000	1.1389	0.0897
6	`m5/A` → `m5/X`	xor2_1	fall	0.1781	1.3170	0.0897
	`m5/X` → `m6/A`	wire s5	fall	0.0000	1.3170	0.0897
7	`m6/A` → `m6/X`	xor2_1	fall	0.1649	1.4819	0.0723
	`m6/X` → `r1/D`	wire s6	fall	0.0000	1.4819	0.0723

The report

Startpoint: a1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
Path Group: stageA
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                    0.1000    0.0000    0.0000 ^ a1/CLK (sky130_fd_sc_hd__dfxtp_1)
     7    0.0286    0.2741    0.4872    0.4872 ^ a1/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 qa1 (net)
                    0.2741    0.0000    0.4872 ^ m1/B (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1173    0.6045 v m1/X (sky130_fd_sc_hd__xor2_1)
                                                 s1 (net)
                    0.0897    0.0000    0.6045 v m2/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    0.7827 v m2/X (sky130_fd_sc_hd__xor2_1)
                                                 s2 (net)
                    0.0897    0.0000    0.7827 v m3/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    0.9608 v m3/X (sky130_fd_sc_hd__xor2_1)
                                                 s3 (net)
                    0.0897    0.0000    0.9608 v m4/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    1.1389 v m4/X (sky130_fd_sc_hd__xor2_1)
                                                 s4 (net)
                    0.0897    0.0000    1.1389 v m5/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    1.3170 v m5/X (sky130_fd_sc_hd__xor2_1)
                                                 s5 (net)
                    0.0897    0.0000    1.3170 v m6/A (sky130_fd_sc_hd__xor2_1)
     1    0.0017    0.0723    0.1649    1.4819 v m6/X (sky130_fd_sc_hd__xor2_1)
                                                 s6 (net)
                    0.0723    0.0000    1.4819 v r1/D (sky130_fd_sc_hd__dfxtp_1)
                                        1.4819   data arrival time

                    0.1000    1.2500    1.2500   clock clk (rise edge)
                              0.4000    1.6500   clock network delay (ideal)
                              0.0000    1.6500   clock reconvergence pessimism
                                        1.6500 ^ r1/CLK (sky130_fd_sc_hd__dfxtp_1)
                             -0.1096    1.5404   library setup time
                                        1.5404   data required time
-------------------------------------------------------------------------------------
                                        1.5404   data required time
                                       -1.4819   data arrival time
-------------------------------------------------------------------------------------
                                        0.0585   slack (MET)

set_clock_latency 0.4 [get_pins {r0/CLK r1/CLK}] on the ideal clock.

Loops give nothing back

The second limit is loops. Follow a path of registers that returns to where it started. Each register's latency is added once as a capture and taken away once as a launch. So the skews around a loop add up to zero: skew can move time between the stages of a loop, but never add any. Ignoring hold, variation and other paths, two stage delays d_a and d_b have a lower period bound (d_a + d_b) / 2.

The MAC's registers and its one loopArrows are data. acc feeds the adder that feeds acc.

A path that skew can help
p → adder → acc: delaying acc gives it time, taken from paths that start at acc.
A common vector latency cancels
acc is a vector. This path crosses different bits; giving every bit the same latency moves both ends equally.

Read the diagram as text

ra, rb: operand registers
multiplier: stage into p
p: product register
adder: acc + p
acc: accumulator

ra, rb → multiplier: data
multiplier → p: data
p → adder: data
adder → acc: sum
acc → adder: acc

R4.5's MAC, mapped to sky130 cells.

At 4.2 ns the MAC's adder stage fails twice. The path from p fails by 0.0797 ns and the loop from acc by 0.0959 ns. Delay all of acc by 0.15 ns and the first path passes at 0.0703 ns, while the loop does not move at all.

Timing pathThe accumulator loop with acc's clock lateThe worst acc → acc path at 4.2 ns, with set_clock_latency 0.15 on all twenty acc clock pins.

_809_ → _827_setup check, latest arrival16 cells

Clock latency
Cell delay
Setup time

Late launch
The launch edge at the acc flop comes 0.15 ns late.
Late capture
So does the capture edge: another acc bit, the same 0.15 ns.
Unchanged
The slack stays at -0.0959 ns, exactly what the loop had with no latency at all.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.1500 ns (ideal). Capture: clk rise edge at 4.2000 ns, latency 0.1500 ns, library setup time −0.0799 ns.

Arrival 4.3659 ns, required 4.2701 ns, slack −0.0959 ns (violated).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`_809_/CLK` → `_809_/Q`	dfrtp_1	fall	0.3700	0.5200	0.0674
	`_809_/Q` → `_607_/A`	wire acc[1]	fall	0.0000	0.5200	0.0674
2	`_607_/A` → `_607_/Y`	xnor2_1	rise	0.2090	0.7290	0.1928
	`_607_/Y` → `_619_/A2`	wire _080_	rise	0.0000	0.7290	0.1928
3	`_619_/A2` → `_619_/Y`	o21ai_0	fall	0.1481	0.8771	0.1149
	`_619_/Y` → `_641_/C`	wire _081_	fall	0.0000	0.8771	0.1149
4	`_641_/C` → `_641_/X`	maj3_1	fall	0.3990	1.2760	0.0920
	`_641_/X` → `_663_/C`	wire _083_	fall	0.0000	1.2760	0.0920
5	`_663_/C` → `_663_/X`	maj3_1	fall	0.3921	1.6682	0.0920
	`_663_/X` → `_685_/C`	wire _085_	fall	0.0000	1.6682	0.0920
6	`_685_/C` → `_685_/X`	maj3_1	fall	0.3921	2.0603	0.0920
	`_685_/X` → `_707_/C`	wire _087_	fall	0.0000	2.0603	0.0920
7	`_707_/C` → `_707_/X`	maj3_1	fall	0.4037	2.4640	0.1013
	`_707_/X` → `_727_/A1`	wire _089_	fall	0.0000	2.4640	0.1013
8	`_727_/A1` → `_727_/Y`	a211oi_1	rise	0.2652	2.7292	0.2531
	`_727_/Y` → `_729_/A3`	wire _093_	rise	0.0000	2.7292	0.2531
9	`_729_/A3` → `_729_/Y`	o31ai_1	fall	0.1414	2.8706	0.0941
	`_729_/Y` → `_731_/A2`	wire _095_	fall	0.0000	2.8706	0.0941
10	`_731_/A2` → `_731_/X`	o211a_1	fall	0.2244	3.0950	0.0449
	`_731_/X` → `_734_/A3`	wire _097_	fall	0.0000	3.0950	0.0449
11	`_734_/A3` → `_734_/Y`	o311ai_0	rise	0.4243	3.5192	0.4921
	`_734_/Y` → `_736_/A3`	wire _100_	rise	0.0000	3.5192	0.4921
12	`_736_/A3` → `_736_/Y`	a31oi_1	fall	0.1878	3.7070	0.1296
	`_736_/Y` → `_737_/A2`	wire _101_	fall	0.0000	3.7070	0.1296
13	`_737_/A2` → `_737_/Y`	a21oi_1	rise	0.2650	3.9720	0.2375
	`_737_/Y` → `_740_/A2`	wire _102_	rise	0.0000	3.9720	0.2375
14	`_740_/A2` → `_740_/Y`	a211oi_1	fall	0.1644	4.1365	0.1196
	`_740_/Y` → `_742_/C`	wire _105_	fall	0.0000	4.1365	0.1196
15	`_742_/C` → `_742_/Y`	nand3_1	rise	0.1214	4.2578	0.0801
	`_742_/Y` → `_748_/B`	wire _107_	rise	0.0000	4.2578	0.0801
16	`_748_/B` → `_748_/Y`	xnor2_1	rise	0.1081	4.3659	0.1022
	`_748_/Y` → `_827_/D`	wire _048_	rise	0.0000	4.3659	0.1022

The report

Startpoint: _809_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _827_ (rising edge-triggered flip-flop clocked by clk)
Path Group: accToAcc
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.0000    0.0000    0.0000   clock clk (rise edge)
                              0.1500    0.1500   clock network delay (ideal)
                    0.0000    0.0000    0.1500 ^ _809_/CLK (sky130_fd_sc_hd__dfrtp_1)
     4    0.0088    0.0674    0.3700    0.5200 v _809_/Q (sky130_fd_sc_hd__dfrtp_1)
                                                 acc[1] (net)
                    0.0674    0.0000    0.5200 v _607_/A (sky130_fd_sc_hd__xnor2_1)
     2    0.0065    0.1928    0.2090    0.7290 ^ _607_/Y (sky130_fd_sc_hd__xnor2_1)
                                                 _080_ (net)
                    0.1928    0.0000    0.7290 ^ _619_/A2 (sky130_fd_sc_hd__o21ai_0)
     2    0.0073    0.1149    0.1481    0.8771 v _619_/Y (sky130_fd_sc_hd__o21ai_0)
                                                 _081_ (net)
                    0.1149    0.0000    0.8771 v _641_/C (sky130_fd_sc_hd__maj3_1)
     2    0.0073    0.0920    0.3990    1.2760 v _641_/X (sky130_fd_sc_hd__maj3_1)
                                                 _083_ (net)
                    0.0920    0.0000    1.2760 v _663_/C (sky130_fd_sc_hd__maj3_1)
     2    0.0073    0.0920    0.3921    1.6682 v _663_/X (sky130_fd_sc_hd__maj3_1)
                                                 _085_ (net)
                    0.0920    0.0000    1.6682 v _685_/C (sky130_fd_sc_hd__maj3_1)
     2    0.0073    0.0920    0.3921    2.0603 v _685_/X (sky130_fd_sc_hd__maj3_1)
                                                 _087_ (net)
                    0.0920    0.0000    2.0603 v _707_/C (sky130_fd_sc_hd__maj3_1)
     3    0.0090    0.1013    0.4037    2.4640 v _707_/X (sky130_fd_sc_hd__maj3_1)
                                                 _089_ (net)
                    0.1013    0.0000    2.4640 v _727_/A1 (sky130_fd_sc_hd__a211oi_1)
     2    0.0052    0.2531    0.2652    2.7292 ^ _727_/Y (sky130_fd_sc_hd__a211oi_1)
                                                 _093_ (net)
                    0.2531    0.0000    2.7292 ^ _729_/A3 (sky130_fd_sc_hd__o31ai_1)
     3    0.0088    0.0941    0.1414    2.8706 v _729_/Y (sky130_fd_sc_hd__o31ai_1)
                                                 _095_ (net)
                    0.0941    0.0000    2.8706 v _731_/A2 (sky130_fd_sc_hd__o211a_1)
     2    0.0038    0.0449    0.2244    3.0950 v _731_/X (sky130_fd_sc_hd__o211a_1)
                                                 _097_ (net)
                    0.0449    0.0000    3.0950 v _734_/A3 (sky130_fd_sc_hd__o311ai_0)
     3    0.0073    0.4921    0.4243    3.5192 ^ _734_/Y (sky130_fd_sc_hd__o311ai_0)
                                                 _100_ (net)
                    0.4921    0.0000    3.5192 ^ _736_/A3 (sky130_fd_sc_hd__a31oi_1)
     2    0.0067    0.1296    0.1878    3.7070 v _736_/Y (sky130_fd_sc_hd__a31oi_1)
                                                 _101_ (net)
                    0.1296    0.0000    3.7070 v _737_/A2 (sky130_fd_sc_hd__a21oi_1)
     3    0.0096    0.2375    0.2650    3.9720 ^ _737_/Y (sky130_fd_sc_hd__a21oi_1)
                                                 _102_ (net)
                    0.2375    0.0000    3.9720 ^ _740_/A2 (sky130_fd_sc_hd__a211oi_1)
     4    0.0109    0.1196    0.1644    4.1365 v _740_/Y (sky130_fd_sc_hd__a211oi_1)
                                                 _105_ (net)
                    0.1196    0.0000    4.1365 v _742_/C (sky130_fd_sc_hd__nand3_1)
     1    0.0047    0.0801    0.1214    4.2578 ^ _742_/Y (sky130_fd_sc_hd__nand3_1)
                                                 _107_ (net)
                    0.0801    0.0000    4.2578 ^ _748_/B (sky130_fd_sc_hd__xnor2_1)
     1    0.0020    0.1022    0.1081    4.3659 ^ _748_/Y (sky130_fd_sc_hd__xnor2_1)
                                                 _048_ (net)
                    0.1022    0.0000    4.3659 ^ _827_/D (sky130_fd_sc_hd__dfrtp_1)
                                        4.3659   data arrival time

                    0.0000    4.2000    4.2000   clock clk (rise edge)
                              0.1500    4.3500   clock network delay (ideal)
                              0.0000    4.3500   clock reconvergence pessimism
                                        4.3500 ^ _827_/CLK (sky130_fd_sc_hd__dfrtp_1)
                             -0.0799    4.2701   library setup time
                                        4.2701   data required time
-------------------------------------------------------------------------------------
                                        4.2701   data required time
                                       -4.3659   data arrival time
-------------------------------------------------------------------------------------
                                       -0.0959   slack (VIOLATED)

OpenSTA 3.1.0 on the bundled MAC netlist, ideal clock, no wires.

The other two paths of this comparison

Timing pathp to acc, with acc's clock late

_793_ → _827_setup check, latest arrival16 cells

Clock latency
Cell delay
Setup time

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 4.2000 ns, latency 0.1500 ns, library setup time −0.0799 ns.

Arrival 4.1997 ns, required 4.2701 ns, slack 0.0703 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`_793_/CLK` → `_793_/Q`	dfrtp_1	fall	0.3716	0.3716	0.0688
	`_793_/Q` → `_607_/B`	wire p[1]	fall	0.0000	0.3716	0.0688
2	`_607_/B` → `_607_/Y`	xnor2_1	rise	0.1911	0.5628	0.1928
	`_607_/Y` → `_619_/A2`	wire _080_	rise	0.0000	0.5628	0.1928
3	`_619_/A2` → `_619_/Y`	o21ai_0	fall	0.1481	0.7109	0.1149
	`_619_/Y` → `_641_/C`	wire _081_	fall	0.0000	0.7109	0.1149
4	`_641_/C` → `_641_/X`	maj3_1	fall	0.3990	1.1098	0.0920
	`_641_/X` → `_663_/C`	wire _083_	fall	0.0000	1.1098	0.0920
5	`_663_/C` → `_663_/X`	maj3_1	fall	0.3921	1.5020	0.0920
	`_663_/X` → `_685_/C`	wire _085_	fall	0.0000	1.5020	0.0920
6	`_685_/C` → `_685_/X`	maj3_1	fall	0.3921	1.8941	0.0920
	`_685_/X` → `_707_/C`	wire _087_	fall	0.0000	1.8941	0.0920
7	`_707_/C` → `_707_/X`	maj3_1	fall	0.4037	2.2978	0.1013
	`_707_/X` → `_727_/A1`	wire _089_	fall	0.0000	2.2978	0.1013
8	`_727_/A1` → `_727_/Y`	a211oi_1	rise	0.2652	2.5630	0.2531
	`_727_/Y` → `_729_/A3`	wire _093_	rise	0.0000	2.5630	0.2531
9	`_729_/A3` → `_729_/Y`	o31ai_1	fall	0.1414	2.7044	0.0941
	`_729_/Y` → `_731_/A2`	wire _095_	fall	0.0000	2.7044	0.0941
10	`_731_/A2` → `_731_/X`	o211a_1	fall	0.2244	2.9288	0.0449
	`_731_/X` → `_734_/A3`	wire _097_	fall	0.0000	2.9288	0.0449
11	`_734_/A3` → `_734_/Y`	o311ai_0	rise	0.4243	3.3530	0.4921
	`_734_/Y` → `_736_/A3`	wire _100_	rise	0.0000	3.3530	0.4921
12	`_736_/A3` → `_736_/Y`	a31oi_1	fall	0.1878	3.5408	0.1296
	`_736_/Y` → `_737_/A2`	wire _101_	fall	0.0000	3.5408	0.1296
13	`_737_/A2` → `_737_/Y`	a21oi_1	rise	0.2650	3.8058	0.2375
	`_737_/Y` → `_740_/A2`	wire _102_	rise	0.0000	3.8058	0.2375
14	`_740_/A2` → `_740_/Y`	a211oi_1	fall	0.1644	3.9703	0.1196
	`_740_/Y` → `_742_/C`	wire _105_	fall	0.0000	3.9703	0.1196
15	`_742_/C` → `_742_/Y`	nand3_1	rise	0.1214	4.0916	0.0801
	`_742_/Y` → `_748_/B`	wire _107_	rise	0.0000	4.0916	0.0801
16	`_748_/B` → `_748_/Y`	xnor2_1	rise	0.1081	4.1997	0.1022
	`_748_/Y` → `_827_/D`	wire _048_	rise	0.0000	4.1997	0.1022

The report

Startpoint: _793_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _827_ (rising edge-triggered flip-flop clocked by clk)
Path Group: pToAcc
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.0000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                    0.0000    0.0000    0.0000 ^ _793_/CLK (sky130_fd_sc_hd__dfrtp_1)
     3    0.0091    0.0688    0.3716    0.3716 v _793_/Q (sky130_fd_sc_hd__dfrtp_1)
                                                 p[1] (net)
                    0.0688    0.0000    0.3716 v _607_/B (sky130_fd_sc_hd__xnor2_1)
     2    0.0065    0.1928    0.1911    0.5628 ^ _607_/Y (sky130_fd_sc_hd__xnor2_1)
                                                 _080_ (net)
                    0.1928    0.0000    0.5628 ^ _619_/A2 (sky130_fd_sc_hd__o21ai_0)
     2    0.0073    0.1149    0.1481    0.7109 v _619_/Y (sky130_fd_sc_hd__o21ai_0)
                                                 _081_ (net)
                    0.1149    0.0000    0.7109 v _641_/C (sky130_fd_sc_hd__maj3_1)
     2    0.0073    0.0920    0.3990    1.1098 v _641_/X (sky130_fd_sc_hd__maj3_1)
                                                 _083_ (net)
                    0.0920    0.0000    1.1098 v _663_/C (sky130_fd_sc_hd__maj3_1)
     2    0.0073    0.0920    0.3921    1.5020 v _663_/X (sky130_fd_sc_hd__maj3_1)
                                                 _085_ (net)
                    0.0920    0.0000    1.5020 v _685_/C (sky130_fd_sc_hd__maj3_1)
     2    0.0073    0.0920    0.3921    1.8941 v _685_/X (sky130_fd_sc_hd__maj3_1)
                                                 _087_ (net)
                    0.0920    0.0000    1.8941 v _707_/C (sky130_fd_sc_hd__maj3_1)
     3    0.0090    0.1013    0.4037    2.2978 v _707_/X (sky130_fd_sc_hd__maj3_1)
                                                 _089_ (net)
                    0.1013    0.0000    2.2978 v _727_/A1 (sky130_fd_sc_hd__a211oi_1)
     2    0.0052    0.2531    0.2652    2.5630 ^ _727_/Y (sky130_fd_sc_hd__a211oi_1)
                                                 _093_ (net)
                    0.2531    0.0000    2.5630 ^ _729_/A3 (sky130_fd_sc_hd__o31ai_1)
     3    0.0088    0.0941    0.1414    2.7044 v _729_/Y (sky130_fd_sc_hd__o31ai_1)
                                                 _095_ (net)
                    0.0941    0.0000    2.7044 v _731_/A2 (sky130_fd_sc_hd__o211a_1)
     2    0.0038    0.0449    0.2244    2.9288 v _731_/X (sky130_fd_sc_hd__o211a_1)
                                                 _097_ (net)
                    0.0449    0.0000    2.9288 v _734_/A3 (sky130_fd_sc_hd__o311ai_0)
     3    0.0073    0.4921    0.4243    3.3530 ^ _734_/Y (sky130_fd_sc_hd__o311ai_0)
                                                 _100_ (net)
                    0.4921    0.0000    3.3530 ^ _736_/A3 (sky130_fd_sc_hd__a31oi_1)
     2    0.0067    0.1296    0.1878    3.5408 v _736_/Y (sky130_fd_sc_hd__a31oi_1)
                                                 _101_ (net)
                    0.1296    0.0000    3.5408 v _737_/A2 (sky130_fd_sc_hd__a21oi_1)
     3    0.0096    0.2375    0.2650    3.8058 ^ _737_/Y (sky130_fd_sc_hd__a21oi_1)
                                                 _102_ (net)
                    0.2375    0.0000    3.8058 ^ _740_/A2 (sky130_fd_sc_hd__a211oi_1)
     4    0.0109    0.1196    0.1644    3.9703 v _740_/Y (sky130_fd_sc_hd__a211oi_1)
                                                 _105_ (net)
                    0.1196    0.0000    3.9703 v _742_/C (sky130_fd_sc_hd__nand3_1)
     1    0.0047    0.0801    0.1214    4.0916 ^ _742_/Y (sky130_fd_sc_hd__nand3_1)
                                                 _107_ (net)
                    0.0801    0.0000    4.0916 ^ _748_/B (sky130_fd_sc_hd__xnor2_1)
     1    0.0020    0.1022    0.1081    4.1997 ^ _748_/Y (sky130_fd_sc_hd__xnor2_1)
                                                 _048_ (net)
                    0.1022    0.0000    4.1997 ^ _827_/D (sky130_fd_sc_hd__dfrtp_1)
                                        4.1997   data arrival time

                    0.0000    4.2000    4.2000   clock clk (rise edge)
                              0.1500    4.3500   clock network delay (ideal)
                              0.0000    4.3500   clock reconvergence pessimism
                                        4.3500 ^ _827_/CLK (sky130_fd_sc_hd__dfrtp_1)
                             -0.0799    4.2701   library setup time
                                        4.2701   data required time
-------------------------------------------------------------------------------------
                                        4.2701   data required time
                                       -4.1997   data arrival time
-------------------------------------------------------------------------------------
                                        0.0703   slack (MET)

The same run: the capture edge moved, the launch edge did not.

Timing pathacc to acc, no latency

_809_ → _827_setup check, latest arrival16 cells

Clock latency
Cell delay
Setup time

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 4.2000 ns, latency 0.0000 ns, library setup time −0.0799 ns.

Arrival 4.2159 ns, required 4.1201 ns, slack −0.0959 ns (violated).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`_809_/CLK` → `_809_/Q`	dfrtp_1	fall	0.3700	0.3700	0.0674
	`_809_/Q` → `_607_/A`	wire acc[1]	fall	0.0000	0.3700	0.0674
2	`_607_/A` → `_607_/Y`	xnor2_1	rise	0.2090	0.5790	0.1928
	`_607_/Y` → `_619_/A2`	wire _080_	rise	0.0000	0.5790	0.1928
3	`_619_/A2` → `_619_/Y`	o21ai_0	fall	0.1481	0.7271	0.1149
	`_619_/Y` → `_641_/C`	wire _081_	fall	0.0000	0.7271	0.1149
4	`_641_/C` → `_641_/X`	maj3_1	fall	0.3990	1.1260	0.0920
	`_641_/X` → `_663_/C`	wire _083_	fall	0.0000	1.1260	0.0920
5	`_663_/C` → `_663_/X`	maj3_1	fall	0.3921	1.5182	0.0920
	`_663_/X` → `_685_/C`	wire _085_	fall	0.0000	1.5182	0.0920
6	`_685_/C` → `_685_/X`	maj3_1	fall	0.3921	1.9103	0.0920
	`_685_/X` → `_707_/C`	wire _087_	fall	0.0000	1.9103	0.0920
7	`_707_/C` → `_707_/X`	maj3_1	fall	0.4037	2.3140	0.1013
	`_707_/X` → `_727_/A1`	wire _089_	fall	0.0000	2.3140	0.1013
8	`_727_/A1` → `_727_/Y`	a211oi_1	rise	0.2652	2.5792	0.2531
	`_727_/Y` → `_729_/A3`	wire _093_	rise	0.0000	2.5792	0.2531
9	`_729_/A3` → `_729_/Y`	o31ai_1	fall	0.1414	2.7206	0.0941
	`_729_/Y` → `_731_/A2`	wire _095_	fall	0.0000	2.7206	0.0941
10	`_731_/A2` → `_731_/X`	o211a_1	fall	0.2244	2.9450	0.0449
	`_731_/X` → `_734_/A3`	wire _097_	fall	0.0000	2.9450	0.0449
11	`_734_/A3` → `_734_/Y`	o311ai_0	rise	0.4243	3.3692	0.4921
	`_734_/Y` → `_736_/A3`	wire _100_	rise	0.0000	3.3692	0.4921
12	`_736_/A3` → `_736_/Y`	a31oi_1	fall	0.1878	3.5570	0.1296
	`_736_/Y` → `_737_/A2`	wire _101_	fall	0.0000	3.5570	0.1296
13	`_737_/A2` → `_737_/Y`	a21oi_1	rise	0.2650	3.8220	0.2375
	`_737_/Y` → `_740_/A2`	wire _102_	rise	0.0000	3.8220	0.2375
14	`_740_/A2` → `_740_/Y`	a211oi_1	fall	0.1644	3.9865	0.1196
	`_740_/Y` → `_742_/C`	wire _105_	fall	0.0000	3.9865	0.1196
15	`_742_/C` → `_742_/Y`	nand3_1	rise	0.1214	4.1078	0.0801
	`_742_/Y` → `_748_/B`	wire _107_	rise	0.0000	4.1078	0.0801
16	`_748_/B` → `_748_/Y`	xnor2_1	rise	0.1081	4.2159	0.1022
	`_748_/Y` → `_827_/D`	wire _048_	rise	0.0000	4.2159	0.1022

The report

Startpoint: _809_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _827_ (rising edge-triggered flip-flop clocked by clk)
Path Group: accToAcc
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.0000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                    0.0000    0.0000    0.0000 ^ _809_/CLK (sky130_fd_sc_hd__dfrtp_1)
     4    0.0088    0.0674    0.3700    0.3700 v _809_/Q (sky130_fd_sc_hd__dfrtp_1)
                                                 acc[1] (net)
                    0.0674    0.0000    0.3700 v _607_/A (sky130_fd_sc_hd__xnor2_1)
     2    0.0065    0.1928    0.2090    0.5790 ^ _607_/Y (sky130_fd_sc_hd__xnor2_1)
                                                 _080_ (net)
                    0.1928    0.0000    0.5790 ^ _619_/A2 (sky130_fd_sc_hd__o21ai_0)
     2    0.0073    0.1149    0.1481    0.7271 v _619_/Y (sky130_fd_sc_hd__o21ai_0)
                                                 _081_ (net)
                    0.1149    0.0000    0.7271 v _641_/C (sky130_fd_sc_hd__maj3_1)
     2    0.0073    0.0920    0.3990    1.1260 v _641_/X (sky130_fd_sc_hd__maj3_1)
                                                 _083_ (net)
                    0.0920    0.0000    1.1260 v _663_/C (sky130_fd_sc_hd__maj3_1)
     2    0.0073    0.0920    0.3921    1.5182 v _663_/X (sky130_fd_sc_hd__maj3_1)
                                                 _085_ (net)
                    0.0920    0.0000    1.5182 v _685_/C (sky130_fd_sc_hd__maj3_1)
     2    0.0073    0.0920    0.3921    1.9103 v _685_/X (sky130_fd_sc_hd__maj3_1)
                                                 _087_ (net)
                    0.0920    0.0000    1.9103 v _707_/C (sky130_fd_sc_hd__maj3_1)
     3    0.0090    0.1013    0.4037    2.3140 v _707_/X (sky130_fd_sc_hd__maj3_1)
                                                 _089_ (net)
                    0.1013    0.0000    2.3140 v _727_/A1 (sky130_fd_sc_hd__a211oi_1)
     2    0.0052    0.2531    0.2652    2.5792 ^ _727_/Y (sky130_fd_sc_hd__a211oi_1)
                                                 _093_ (net)
                    0.2531    0.0000    2.5792 ^ _729_/A3 (sky130_fd_sc_hd__o31ai_1)
     3    0.0088    0.0941    0.1414    2.7206 v _729_/Y (sky130_fd_sc_hd__o31ai_1)
                                                 _095_ (net)
                    0.0941    0.0000    2.7206 v _731_/A2 (sky130_fd_sc_hd__o211a_1)
     2    0.0038    0.0449    0.2244    2.9450 v _731_/X (sky130_fd_sc_hd__o211a_1)
                                                 _097_ (net)
                    0.0449    0.0000    2.9450 v _734_/A3 (sky130_fd_sc_hd__o311ai_0)
     3    0.0073    0.4921    0.4243    3.3692 ^ _734_/Y (sky130_fd_sc_hd__o311ai_0)
                                                 _100_ (net)
                    0.4921    0.0000    3.3692 ^ _736_/A3 (sky130_fd_sc_hd__a31oi_1)
     2    0.0067    0.1296    0.1878    3.5570 v _736_/Y (sky130_fd_sc_hd__a31oi_1)
                                                 _101_ (net)
                    0.1296    0.0000    3.5570 v _737_/A2 (sky130_fd_sc_hd__a21oi_1)
     3    0.0096    0.2375    0.2650    3.8220 ^ _737_/Y (sky130_fd_sc_hd__a21oi_1)
                                                 _102_ (net)
                    0.2375    0.0000    3.8220 ^ _740_/A2 (sky130_fd_sc_hd__a211oi_1)
     4    0.0109    0.1196    0.1644    3.9865 v _740_/Y (sky130_fd_sc_hd__a211oi_1)
                                                 _105_ (net)
                    0.1196    0.0000    3.9865 v _742_/C (sky130_fd_sc_hd__nand3_1)
     1    0.0047    0.0801    0.1214    4.1078 ^ _742_/Y (sky130_fd_sc_hd__nand3_1)
                                                 _107_ (net)
                    0.0801    0.0000    4.1078 ^ _748_/B (sky130_fd_sc_hd__xnor2_1)
     1    0.0020    0.1022    0.1081    4.2159 ^ _748_/Y (sky130_fd_sc_hd__xnor2_1)
                                                 _048_ (net)
                    0.1022    0.0000    4.2159 ^ _827_/D (sky130_fd_sc_hd__dfrtp_1)
                                        4.2159   data arrival time

                    0.0000    4.2000    4.2000   clock clk (rise edge)
                              0.0000    4.2000   clock network delay (ideal)
                              0.0000    4.2000   clock reconvergence pessimism
                                        4.2000 ^ _827_/CLK (sky130_fd_sc_hd__dfrtp_1)
                             -0.0799    4.1201   library setup time
                                        4.1201   data required time
-------------------------------------------------------------------------------------
                                        4.1201   data required time
                                       -4.2159   data arrival time
-------------------------------------------------------------------------------------
                                       -0.0959   slack (VIOLATED)

The loop with an ideal clock and no latency.

With one shared latency for all accumulator bits, this path still needs 4.2959 ns. This is not a bound for arbitrary per-bit skew. Retiming can move registers within a loop while preserving its total register count; skew can redistribute stage budgets, but adds no total time around a cycle.

Building the delay

The third limit is that an ideal latency costs nothing, and silicon does. The delay must be real cells on R's clock branch. Here two clkdlybuf4s18_1 cells, clock delay buffers, stand in for the 0.4 ns of the SDC.

Timing pathStage A with R's clock through two delay buffersA propagated clock: every flop's latency is its real clock path. R's clock passes dl1 and dl2 (clkdlybuf4s18_1).

a1 → r1setup check, latest arrival7 cells

Clock latency
Cell delay
Setup time

Launch
a0 is clocked straight from the port, so its launch latency is 0.0000 ns.
Built latency
R's clock arrives 0.3935 ns late, through the two delay buffers.
Met
Stage A meets setup with the built delay, at a slack of 0.0399 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns. Capture: clk rise edge at 1.2500 ns, latency 0.3935 ns, library setup time −0.1217 ns.

Arrival 1.4819 ns, required 1.5218 ns, slack 0.0399 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`a1/CLK` → `a1/Q`	dfxtp_1	rise	0.4872	0.4872	0.2741
	`a1/Q` → `m1/B`	wire qa1	rise	0.0000	0.4872	0.2741
2	`m1/B` → `m1/X`	xor2_1	fall	0.1173	0.6045	0.0897
	`m1/X` → `m2/A`	wire s1	fall	0.0000	0.6045	0.0897
3	`m2/A` → `m2/X`	xor2_1	fall	0.1781	0.7827	0.0897
	`m2/X` → `m3/A`	wire s2	fall	0.0000	0.7827	0.0897
4	`m3/A` → `m3/X`	xor2_1	fall	0.1781	0.9608	0.0897
	`m3/X` → `m4/A`	wire s3	fall	0.0000	0.9608	0.0897
5	`m4/A` → `m4/X`	xor2_1	fall	0.1781	1.1389	0.0897
	`m4/X` → `m5/A`	wire s4	fall	0.0000	1.1389	0.0897
6	`m5/A` → `m5/X`	xor2_1	fall	0.1781	1.3170	0.0897
	`m5/X` → `m6/A`	wire s5	fall	0.0000	1.3170	0.0897
7	`m6/A` → `m6/X`	xor2_1	fall	0.1649	1.4819	0.0723
	`m6/X` → `r1/D`	wire s6	fall	0.0000	1.4819	0.0723

The report

Startpoint: a1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
Path Group: stageA
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     4    0.0079    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ a1/CLK (sky130_fd_sc_hd__dfxtp_1)
     7    0.0286    0.2741    0.4872    0.4872 ^ a1/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 qa1 (net)
                    0.2741    0.0000    0.4872 ^ m1/B (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1173    0.6045 v m1/X (sky130_fd_sc_hd__xor2_1)
                                                 s1 (net)
                    0.0897    0.0000    0.6045 v m2/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    0.7827 v m2/X (sky130_fd_sc_hd__xor2_1)
                                                 s2 (net)
                    0.0897    0.0000    0.7827 v m3/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    0.9608 v m3/X (sky130_fd_sc_hd__xor2_1)
                                                 s3 (net)
                    0.0897    0.0000    0.9608 v m4/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    1.1389 v m4/X (sky130_fd_sc_hd__xor2_1)
                                                 s4 (net)
                    0.0897    0.0000    1.1389 v m5/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    1.3170 v m5/X (sky130_fd_sc_hd__xor2_1)
                                                 s5 (net)
                    0.0897    0.0000    1.3170 v m6/A (sky130_fd_sc_hd__xor2_1)
     1    0.0017    0.0723    0.1649    1.4819 v m6/X (sky130_fd_sc_hd__xor2_1)
                                                 s6 (net)
                    0.0723    0.0000    1.4819 v r1/D (sky130_fd_sc_hd__dfxtp_1)
                                        1.4819   data arrival time

                              1.2500    1.2500   clock clk (rise edge)
                              0.0000    1.2500   clock source latency
     4    0.0079    0.1000    0.0000    1.2500 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    1.2500 ^ dl1/A (sky130_fd_sc_hd__clkdlybuf4s18_1)
     1    0.0023    0.0352    0.2029    1.4529 ^ dl1/X (sky130_fd_sc_hd__clkdlybuf4s18_1)
                                                 rc1 (net)
                    0.0352    0.0000    1.4529 ^ dl2/A (sky130_fd_sc_hd__clkdlybuf4s18_1)
     2    0.0038    0.0482    0.1906    1.6435 ^ dl2/X (sky130_fd_sc_hd__clkdlybuf4s18_1)
                                                 rc2 (net)
                    0.0482    0.0000    1.6435 ^ r1/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    1.6435   clock reconvergence pessimism
                             -0.1217    1.5218   library setup time
                                        1.5218   data required time
-------------------------------------------------------------------------------------
                                        1.5218   data required time
                                       -1.4819   data arrival time
-------------------------------------------------------------------------------------
                                        0.0399   slack (MET)

OpenSTA 3.1.0, propagated clock with a 0.1 ns slew at the port.

Hold into R with the built delay

Timing pathHold into R, built delay

a0 → r0hold check, earliest arrival2 cells

Clock latency
Cell delay
Hold time

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns. Capture: clk rise edge at 0.0000 ns, latency 0.3935 ns, library hold time −0.0293 ns.

Arrival 0.4517 ns, required 0.3642 ns, slack 0.0875 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`a0/CLK` → `a0/Q`	dfxtp_1	rise	0.3418	0.3418	0.0703
	`a0/Q` → `g0/A`	wire qa0	rise	0.0000	0.3418	0.0703
2	`g0/A` → `g0/X`	and2_1	rise	0.1099	0.4517	0.0378
	`g0/X` → `r0/D`	wire p0	rise	0.0000	0.4517	0.0378

The report

Startpoint: a0 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r0 (rising edge-triggered flip-flop clocked by clk)
Path Group: intoR
Path Type: min

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     4    0.0079    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ a0/CLK (sky130_fd_sc_hd__dfxtp_1)
     2    0.0060    0.0703    0.3418    0.3418 ^ a0/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 qa0 (net)
                    0.0703    0.0000    0.3418 ^ g0/A (sky130_fd_sc_hd__and2_1)
     1    0.0017    0.0378    0.1099    0.4517 ^ g0/X (sky130_fd_sc_hd__and2_1)
                                                 p0 (net)
                    0.0378    0.0000    0.4517 ^ r0/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.4517   data arrival time

                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     4    0.0079    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ dl1/A (sky130_fd_sc_hd__clkdlybuf4s18_1)
     1    0.0023    0.0352    0.2029    0.2029 ^ dl1/X (sky130_fd_sc_hd__clkdlybuf4s18_1)
                                                 rc1 (net)
                    0.0352    0.0000    0.2029 ^ dl2/A (sky130_fd_sc_hd__clkdlybuf4s18_1)
     2    0.0038    0.0482    0.1906    0.3935 ^ dl2/X (sky130_fd_sc_hd__clkdlybuf4s18_1)
                                                 rc2 (net)
                    0.0482    0.0000    0.3935 ^ r0/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    0.3935   clock reconvergence pessimism
                             -0.0293    0.3642   library hold time
                                        0.3642   data required time
-------------------------------------------------------------------------------------
                                        0.3642   data required time
                                       -0.4517   data arrival time
-------------------------------------------------------------------------------------
                                        0.0875   slack (MET)

The same run, the shortest path into R.

The built latency is 0.3935 ns, close to the target, and hold into R keeps 0.0875 ns. Cells come in steps, so the latency is whatever a chain of real cells gives. Each clock path that the launch and capture do not share also widens under on-chip variation (L2.9). A chosen ±5 % derate on 0.39 ns moves it by about 0.02 ns, out of a 0.13 ns window.

The pinned OpenROAD's clock_tree_synthesis balances its tree; its options include none that schedules skew. So here you set the target by hand and build it with cells.

Asked in interviews

What is useful skew?
A clock latency difference introduced on purpose. Delaying the clock of a register gives the stage that ends there more setup time and takes the same time from the stage that starts there.
Does positive skew help setup or hold?
With skew = L_capture − L_launch, positive skew helps setup and hurts hold by the same amount. So useful skew is always checked against the shortest path into the delayed register.
Can useful skew fix a path inside a loop?
Yes, by borrowing time from another stage, subject to hold. The total skew around a loop is zero. A true same-flop self-loop gains nothing.
What are the risks of useful skew?
Hold violations on short paths into the delayed register, extra clock cells and power, and more on-chip variation on the clock paths launch and capture do not share.

Try it

This is the pipeline with R's clock 0.4 ns late. Run it: worst setup slack 0.0585 ns, worst hold slack 0.0742 ns. Open Paths to see stage A, stage B and hold into R.

Change the latency to 0.5 and predict which check fails before you run. Then build the delay: delete the latency line, add set_propagated_clock [all_clocks] and set_input_transition 0.1 [get_ports clk], and put clock delay buffers such as sky130_fd_sc_hd__clkdlybuf4s18_1 between clk and the CLK pins of r0 and r1 in the netlist. Try one clkdlybuf4s50_1 instead.

STAOpenSTA in OpenROAD 26Q2 · sky130hd tt_025C_1v80 Liberty · simulator service

Edit the constraints or the netlist, then run

Expected: WNS 0.0585 ns worst minimum slack 0.0742 ns

Check yourself

Predict the outputThe MAC at 4.2 ns, with every acc clock pin 0.15 ns late. What worst setup slack (WNS) does OpenSTA report, in ns?

create_clock -name clk -period 4.2 [get_ports clk]
set_clock_latency 0.15 [get_pins {_808_/CLK _809_/CLK _810_/CLK _811_/CLK _812_/CLK _813_/CLK _814_/CLK _815_/CLK _816_/CLK _817_/CLK _818_/CLK _819_/CLK _820_/CLK _821_/CLK _822_/CLK _823_/CLK _824_/CLK _825_/CLK _826_/CLK _827_/CLK}]
group_path -name pToAcc -from [get_pins {_792_/CLK _793_/CLK _794_/CLK _795_/CLK _796_/CLK _797_/CLK _798_/CLK _799_/CLK _800_/CLK _801_/CLK _802_/CLK _803_/CLK _804_/CLK _805_/CLK _806_/CLK _807_/CLK}] -to [get_pins {_808_/D _809_/D _810_/D _811_/D _812_/D _813_/D _814_/D _815_/D _816_/D _817_/D _818_/D _819_/D _820_/D _821_/D _822_/D _823_/D _824_/D _825_/D _826_/D _827_/D}]
group_path -name accToAcc -from [get_pins {_808_/CLK _809_/CLK _810_/CLK _811_/CLK _812_/CLK _813_/CLK _814_/CLK _815_/CLK _816_/CLK _817_/CLK _818_/CLK _819_/CLK _820_/CLK _821_/CLK _822_/CLK _823_/CLK _824_/CLK _825_/CLK _826_/CLK _827_/CLK}] -to [get_pins {_808_/D _809_/D _810_/D _811_/D _812_/D _813_/D _814_/D _815_/D _816_/D _817_/D _818_/D _819_/D _820_/D _821_/D _822_/D _823_/D _824_/D _825_/D _826_/D _827_/D}]

ConceptIn a pipeline A → R → B, you delay R's clock by 0.2 ns. What changes?

Both setups gain 0.2 ns, because the whole pipeline now has more timeA → R setup loses 0.2 ns, R → B setup gains 0.2 ns, R → B hold loses 0.2 nsA → R setup gains 0.2 ns, R → B setup loses 0.2 ns, A → R hold loses 0.2 nsA → R setup gains 0.2 ns and nothing else moves, since only R changed

ConceptStage X → Y fails setup by 0.1 ns; stage Y → Z has 0.5 ns to spare. Which clock do you delay, and by about how much?

X and Z together, by 0.3 ns, so Y sees a balanced clockZ, by 0.1 ns, so the whole pipeline after Y shifts togetherX, by 0.1 ns, so the data leaves X later and arrives in timeY, by 0.1 to 0.5 ns, if the shortest path into Y still meets hold

ConceptTwo registers form a loop. The stage from the first to the second needs 1.4 ns and the stage back needs 0.8 ns, each including clock-to-Q and setup. Ignoring hold, uncertainty and other paths, what is the shortest period with unrestricted skew?

1.1 ns0.8 ns1.4 ns2.2 ns

ConceptWhy is 0.4 ns of skew built from clock delay buffers riskier than set_clock_latency 0.4 on an ideal clock?

Clock delay buffers are slower at the fast corner, which breaks setupThe cells add a clock path that only one side has, and its delay variesAn SDC latency also delays the launch flops, which the built cells do notDelay buffers add jitter that the clock uncertainty no longer covers

Remember

Delaying a register's clock gives the stage that ends there more setup time and takes the same from the stage that starts there.
Hold into the delayed register shrinks by the same amount, so the shortest path into it sets the upper limit.
Around a register cycle skew sums to zero. A true same-flop self-loop gains nothing; vector feedback needs a bit-level path analysis.
The skew must be built from real clock cells, in steps, with variation on the branch the other side does not share.