Clock gating cells in the tree

Read sky130's clock gating cell as a timed library cell, see why its enable path loses time when the cell sits near the clock root, and watch CTS build the tree through it.

Lesson: L5.6
Time: 25 min
Runs on: OpenROAD
Check: 5 questions

A designer gated two flops with an ICG placed right after the clock root. Timed with the real clock tree, the enable path into the ICG failed setup by 0.1466 ns. The same enable logic into a second ICG, placed near the leaves, met timing with 0.0715 ns to spare.

Timing pathThe enable path into the ICG near the rootFlop ef launches; four gates make en; the check is at icg_root/GATE. The clock is propagated through the hand-built tree.

ef → icg_rootsetup check, latest arrival5 cells

Clock latency
Cell delay
Setup time

A leaf launches
ef sits three buffers down the tree: its clock arrives at 0.4562 ns.
Near the root
The ICG takes its clock right after the root buffer, at 0.1440 ns.
Violated
The capture edge is 0.3122 ns earlier than the launch edge. Slack -0.1466 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.4562 ns. Capture: clk rise edge at 1.0000 ns, latency 0.1440 ns, library setup time −0.1411 ns.

Arrival 1.1495 ns, required 1.0028 ns, slack −0.1466 ns (violated).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`ef/CLK` → `ef/Q`	dfxtp_1	fall	0.3025	0.7587	0.0345
	`ef/Q` → `e1/A`	wire eq	fall	0.0000	0.7587	0.0345
2	`e1/A` → `e1/Y`	inv_1	rise	0.0417	0.8004	0.0308
	`e1/Y` → `e2/A`	wire n1	rise	0.0000	0.8004	0.0308
3	`e2/A` → `e2/Y`	nand2_1	fall	0.0366	0.8369	0.0272
	`e2/Y` → `e3/A`	wire n2	fall	0.0000	0.8369	0.0272
4	`e3/A` → `e3/Y`	nor2_1	rise	0.1113	0.9482	0.1078
	`e3/Y` → `e4/A`	wire n3	rise	0.0000	0.9482	0.1078
5	`e4/A` → `e4/X`	xor2_1	rise	0.2013	1.1495	0.1911
	`e4/X` → `icg_root/GATE`	wire en	rise	0.0000	1.1495	0.1911

The report

Startpoint: ef (rising edge-triggered flip-flop clocked by clk)
Endpoint: icg_root (rising clock gating-check end-point clocked by clk)
Path Group: gateRoot
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0065    0.0392    0.1440    0.1440 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0392    0.0000    0.1440 ^ ub1/A (sky130_fd_sc_hd__clkbuf_4)
     1    0.0022    0.0272    0.1082    0.2522 ^ ub1/X (sky130_fd_sc_hd__clkbuf_4)
                                                 u1 (net)
                    0.0272    0.0000    0.2522 ^ ub2/A (sky130_fd_sc_hd__clkbuf_1)
     2    0.0065    0.0876    0.1039    0.3560 ^ ub2/X (sky130_fd_sc_hd__clkbuf_1)
                                                 u2 (net)
                    0.0876    0.0000    0.3560 ^ ub3/A (sky130_fd_sc_hd__clkbuf_1)
     2    0.0038    0.0568    0.1002    0.4562 ^ ub3/X (sky130_fd_sc_hd__clkbuf_1)
                                                 u3 (net)
                    0.0568    0.0000    0.4562 ^ ef/CLK (sky130_fd_sc_hd__dfxtp_1)
     2    0.0044    0.0345    0.3025    0.7587 v ef/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 eq (net)
                    0.0345    0.0000    0.7587 v e1/A (sky130_fd_sc_hd__inv_1)
     1    0.0024    0.0308    0.0417    0.8004 ^ e1/Y (sky130_fd_sc_hd__inv_1)
                                                 n1 (net)
                    0.0308    0.0000    0.8004 ^ e2/A (sky130_fd_sc_hd__nand2_1)
     1    0.0023    0.0272    0.0366    0.8369 v e2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0272    0.0000    0.8369 v e3/A (sky130_fd_sc_hd__nor2_1)
     1    0.0045    0.1078    0.1113    0.9482 ^ e3/Y (sky130_fd_sc_hd__nor2_1)
                                                 n3 (net)
                    0.1078    0.0000    0.9482 ^ e4/A (sky130_fd_sc_hd__xor2_1)
     3    0.0070    0.1911    0.2013    1.1495 ^ e4/X (sky130_fd_sc_hd__xor2_1)
                                                 en (net)
                    0.1911    0.0000    1.1495 ^ icg_root/GATE (sky130_fd_sc_hd__dlclkp_1)
                                        1.1495   data arrival time

                              1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock source latency
     1    0.0022    0.1000    0.0000    1.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0065    0.0392    0.1440    1.1440 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0392    0.0000    1.1440 ^ icg_root/CLK (sky130_fd_sc_hd__dlclkp_1)
                              0.0000    1.1440   clock reconvergence pessimism
                             -0.1411    1.0028   library setup time
                                        1.0028   data required time
-------------------------------------------------------------------------------------
                                        1.0028   data required time
                                       -1.1495   data arrival time
-------------------------------------------------------------------------------------
                                       -0.1466   slack (VIOLATED)

OpenSTA 3.1.0, sky130_fd_sc_hd tt library, propagated 1 ns clock with a 0.1 ns slew at the port, no wires.

The enable logic was no slower in the first case; the edge that checks it came earlier.

The ICG is a timed cell

The RTL lesson R2.3 built the integrated clock gating cell (ICG) from a latch and an AND gate. It also showed why the latch keeps the gated clock free of glitches. sky130 has the cell: dlclkp_1, with pins GATE (the enable), CLK and GCLK (the gated clock). Its Liberty model says the same thing in data. A state table lets the internal node follow GATE while CLK is low and hold while CLK is high, and GCLK is CLK AND that node.

Cell	Area	Pins	Use
dlclkp_1	17.52 µm²	GATE 1.778 fF, CLK 4.151 fF, GCLK	clock gate
sdlclkp_1	18.77 µm²	GATE, SCE 1.829 fF, CLK, GCLK	clock gate with scan enable
mux2_1	11.26 µm²	A0, A1, S, X	one enable bit, per flop
dfrtp_1	25.02 µm²	D, CLK, RESET_B, Q	the MAC's flop

From the pinned sky130_fd_sc_hd tt Liberty. One ICG replaces an enable mux at every flop it gates.

sdlclkp adds SCE, a scan enable. During test SCE forces the gated clock to run, so the scan chain shifts whatever the functional enable says.

The Liberty also gives GATE a setup and a hold check against the rising CLK, like a flop's D pin. At the fastest slews the setup is 0.1009 ns and the hold -0.0542 ns. Across the table the setup runs from 0.0417 to 0.3241 ns. So the enable is a timed path that ends at the ICG. Tools call it the clock gating check.

Where the ICG sits sets the skew

An ICG is part of the clock tree: its CLK pin is upstream of every flop it gates. The flop that launches the enable sits at a leaf. In this tree the enable check has a capture latency L_icg that is smaller than the launch latency L_leaf. With the site's sign, its skew L_icg − L_leaf is negative, and negative skew costs setup.

Two ICGs in one treeArrows are the clock, except en, the enable from ef. Both ICGs check the same en.

Near the root
icg_root sees the edge at 0.1440 ns, ef at 0.4562 ns: skew -0.3122 ns.
Near the leaves
icg_leaf shares two buffers with ef and sees the edge at 0.3560 ns: skew -0.1002 ns.

Read the diagram as text

root clkbuf_4: after the port
icg_root: CLK at the root
ub1 → ub2: two buffers
icg_leaf: CLK one level up
ub3 → ef: launches en
fa0, fa1: behind 3 buffers
fb0, fb1: behind 1 buffer

root clkbuf_4 → icg_root: CLK
root clkbuf_4 → ub1 → ub2: clock
ub1 → ub2 → icg_leaf: CLK
ub1 → ub2 → ub3 → ef: clock
icg_root → fa0, fa1: GCLK
icg_leaf → fb0, fb1: GCLK
ub3 → ef → icg_leaf: en

Latencies from the two paths below. Closer to the root gates more of the tree, and costs the enable more time.

Enable endpoint	Launch latency	Capture latency	Arrival	Setup	Slack
icg_root/GATE	0.4562 ns	0.1440 ns	1.1495 ns	0.1411 ns	-0.1466 ns
icg_leaf/GATE	0.4562 ns	0.3560 ns	1.1495 ns	0.1350 ns	0.0715 ns
mf/D through mx	0.4562 ns	0.4562 ns	1.4786 ns	0.1101 ns	-0.1325 ns

One OpenSTA run of the tree above at 1.0 ns: the same enable logic into three endpoints.

Moving the ICG one level above the leaves wins back 0.2181 ns. The price is power: an ICG near the root stops more clock buffers when the enable is low. The enable mux has no skew to pay, but it pays its own delay, 0.3291 ns from S to X here, in front of every flop.

The two other enable paths

Timing pathEnable into the ICG near the leaves

ef → icg_leafsetup check, latest arrival5 cells

Clock latency
Cell delay
Setup time

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.4562 ns. Capture: clk rise edge at 1.0000 ns, latency 0.3560 ns, library setup time −0.1350 ns.

Arrival 1.1495 ns, required 1.2210 ns, slack 0.0715 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`ef/CLK` → `ef/Q`	dfxtp_1	fall	0.3025	0.7587	0.0345
	`ef/Q` → `e1/A`	wire eq	fall	0.0000	0.7587	0.0345
2	`e1/A` → `e1/Y`	inv_1	rise	0.0417	0.8004	0.0308
	`e1/Y` → `e2/A`	wire n1	rise	0.0000	0.8004	0.0308
3	`e2/A` → `e2/Y`	nand2_1	fall	0.0366	0.8369	0.0272
	`e2/Y` → `e3/A`	wire n2	fall	0.0000	0.8369	0.0272
4	`e3/A` → `e3/Y`	nor2_1	rise	0.1113	0.9482	0.1078
	`e3/Y` → `e4/A`	wire n3	rise	0.0000	0.9482	0.1078
5	`e4/A` → `e4/X`	xor2_1	rise	0.2013	1.1495	0.1911
	`e4/X` → `icg_leaf/GATE`	wire en	rise	0.0000	1.1495	0.1911

The report

Startpoint: ef (rising edge-triggered flip-flop clocked by clk)
Endpoint: icg_leaf (rising clock gating-check end-point clocked by clk)
Path Group: gateLeaf
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0065    0.0392    0.1440    0.1440 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0392    0.0000    0.1440 ^ ub1/A (sky130_fd_sc_hd__clkbuf_4)
     1    0.0022    0.0272    0.1082    0.2522 ^ ub1/X (sky130_fd_sc_hd__clkbuf_4)
                                                 u1 (net)
                    0.0272    0.0000    0.2522 ^ ub2/A (sky130_fd_sc_hd__clkbuf_1)
     2    0.0065    0.0876    0.1039    0.3560 ^ ub2/X (sky130_fd_sc_hd__clkbuf_1)
                                                 u2 (net)
                    0.0876    0.0000    0.3560 ^ ub3/A (sky130_fd_sc_hd__clkbuf_1)
     2    0.0038    0.0568    0.1002    0.4562 ^ ub3/X (sky130_fd_sc_hd__clkbuf_1)
                                                 u3 (net)
                    0.0568    0.0000    0.4562 ^ ef/CLK (sky130_fd_sc_hd__dfxtp_1)
     2    0.0044    0.0345    0.3025    0.7587 v ef/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 eq (net)
                    0.0345    0.0000    0.7587 v e1/A (sky130_fd_sc_hd__inv_1)
     1    0.0024    0.0308    0.0417    0.8004 ^ e1/Y (sky130_fd_sc_hd__inv_1)
                                                 n1 (net)
                    0.0308    0.0000    0.8004 ^ e2/A (sky130_fd_sc_hd__nand2_1)
     1    0.0023    0.0272    0.0366    0.8369 v e2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0272    0.0000    0.8369 v e3/A (sky130_fd_sc_hd__nor2_1)
     1    0.0045    0.1078    0.1113    0.9482 ^ e3/Y (sky130_fd_sc_hd__nor2_1)
                                                 n3 (net)
                    0.1078    0.0000    0.9482 ^ e4/A (sky130_fd_sc_hd__xor2_1)
     3    0.0070    0.1911    0.2013    1.1495 ^ e4/X (sky130_fd_sc_hd__xor2_1)
                                                 en (net)
                    0.1911    0.0000    1.1495 ^ icg_leaf/GATE (sky130_fd_sc_hd__dlclkp_1)
                                        1.1495   data arrival time

                              1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock source latency
     1    0.0022    0.1000    0.0000    1.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0065    0.0392    0.1440    1.1440 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0392    0.0000    1.1440 ^ ub1/A (sky130_fd_sc_hd__clkbuf_4)
     1    0.0022    0.0272    0.1082    1.2522 ^ ub1/X (sky130_fd_sc_hd__clkbuf_4)
                                                 u1 (net)
                    0.0272    0.0000    1.2522 ^ ub2/A (sky130_fd_sc_hd__clkbuf_1)
     2    0.0065    0.0876    0.1039    1.3560 ^ ub2/X (sky130_fd_sc_hd__clkbuf_1)
                                                 u2 (net)
                    0.0876    0.0000    1.3560 ^ icg_leaf/CLK (sky130_fd_sc_hd__dlclkp_1)
                              0.0000    1.3560   clock reconvergence pessimism
                             -0.1350    1.2210   library setup time
                                        1.2210   data required time
-------------------------------------------------------------------------------------
                                        1.2210   data required time
                                       -1.1495   data arrival time
-------------------------------------------------------------------------------------
                                        0.0715   slack (MET)

The same run: a later capture edge.

Timing pathEnable into a flop through a mux

ef → mfsetup check, latest arrival6 cells

Clock latency
Cell delay
Setup time

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.4562 ns. Capture: clk rise edge at 1.0000 ns, latency 0.4562 ns, library setup time −0.1101 ns.

Arrival 1.4786 ns, required 1.3461 ns, slack −0.1325 ns (violated).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`ef/CLK` → `ef/Q`	dfxtp_1	fall	0.3025	0.7587	0.0345
	`ef/Q` → `e1/A`	wire eq	fall	0.0000	0.7587	0.0345
2	`e1/A` → `e1/Y`	inv_1	rise	0.0417	0.8004	0.0308
	`e1/Y` → `e2/A`	wire n1	rise	0.0000	0.8004	0.0308
3	`e2/A` → `e2/Y`	nand2_1	fall	0.0366	0.8369	0.0272
	`e2/Y` → `e3/A`	wire n2	fall	0.0000	0.8369	0.0272
4	`e3/A` → `e3/Y`	nor2_1	rise	0.1113	0.9482	0.1078
	`e3/Y` → `e4/A`	wire n3	rise	0.0000	0.9482	0.1078
5	`e4/A` → `e4/X`	xor2_1	rise	0.2013	1.1495	0.1911
	`e4/X` → `mx/S`	wire en	rise	0.0000	1.1495	0.1911
6	`mx/S` → `mx/X`	mux2_1	fall	0.3291	1.4786	0.0503
	`mx/X` → `mf/D`	wire dm	fall	0.0000	1.4786	0.0503

The report

Startpoint: ef (rising edge-triggered flip-flop clocked by clk)
Endpoint: mf (rising edge-triggered flip-flop clocked by clk)
Path Group: mux
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock source latency
     1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0065    0.0392    0.1440    0.1440 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0392    0.0000    0.1440 ^ ub1/A (sky130_fd_sc_hd__clkbuf_4)
     1    0.0022    0.0272    0.1082    0.2522 ^ ub1/X (sky130_fd_sc_hd__clkbuf_4)
                                                 u1 (net)
                    0.0272    0.0000    0.2522 ^ ub2/A (sky130_fd_sc_hd__clkbuf_1)
     2    0.0065    0.0876    0.1039    0.3560 ^ ub2/X (sky130_fd_sc_hd__clkbuf_1)
                                                 u2 (net)
                    0.0876    0.0000    0.3560 ^ ub3/A (sky130_fd_sc_hd__clkbuf_1)
     2    0.0038    0.0568    0.1002    0.4562 ^ ub3/X (sky130_fd_sc_hd__clkbuf_1)
                                                 u3 (net)
                    0.0568    0.0000    0.4562 ^ ef/CLK (sky130_fd_sc_hd__dfxtp_1)
     2    0.0044    0.0345    0.3025    0.7587 v ef/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 eq (net)
                    0.0345    0.0000    0.7587 v e1/A (sky130_fd_sc_hd__inv_1)
     1    0.0024    0.0308    0.0417    0.8004 ^ e1/Y (sky130_fd_sc_hd__inv_1)
                                                 n1 (net)
                    0.0308    0.0000    0.8004 ^ e2/A (sky130_fd_sc_hd__nand2_1)
     1    0.0023    0.0272    0.0366    0.8369 v e2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0272    0.0000    0.8369 v e3/A (sky130_fd_sc_hd__nor2_1)
     1    0.0045    0.1078    0.1113    0.9482 ^ e3/Y (sky130_fd_sc_hd__nor2_1)
                                                 n3 (net)
                    0.1078    0.0000    0.9482 ^ e4/A (sky130_fd_sc_hd__xor2_1)
     3    0.0070    0.1911    0.2013    1.1495 ^ e4/X (sky130_fd_sc_hd__xor2_1)
                                                 en (net)
                    0.1911    0.0000    1.1495 ^ mx/S (sky130_fd_sc_hd__mux2_1)
     1    0.0017    0.0503    0.3291    1.4786 v mx/X (sky130_fd_sc_hd__mux2_1)
                                                 dm (net)
                    0.0503    0.0000    1.4786 v mf/D (sky130_fd_sc_hd__dfxtp_1)
                                        1.4786   data arrival time

                              1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock source latency
     1    0.0022    0.1000    0.0000    1.0000 ^ clk (in)
                                                 clk (net)
                    0.1000    0.0000    1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
     2    0.0065    0.0392    0.1440    1.1440 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                 cr (net)
                    0.0392    0.0000    1.1440 ^ ub1/A (sky130_fd_sc_hd__clkbuf_4)
     1    0.0022    0.0272    0.1082    1.2522 ^ ub1/X (sky130_fd_sc_hd__clkbuf_4)
                                                 u1 (net)
                    0.0272    0.0000    1.2522 ^ ub2/A (sky130_fd_sc_hd__clkbuf_1)
     2    0.0065    0.0876    0.1039    1.3560 ^ ub2/X (sky130_fd_sc_hd__clkbuf_1)
                                                 u2 (net)
                    0.0876    0.0000    1.3560 ^ ub3/A (sky130_fd_sc_hd__clkbuf_1)
     2    0.0038    0.0568    0.1002    1.4562 ^ ub3/X (sky130_fd_sc_hd__clkbuf_1)
                                                 u3 (net)
                    0.0568    0.0000    1.4562 ^ mf/CLK (sky130_fd_sc_hd__dfxtp_1)
                              0.0000    1.4562   clock reconvergence pessimism
                             -0.1101    1.3461   library setup time
                                        1.3461   data required time
-------------------------------------------------------------------------------------
                                        1.3461   data required time
                                       -1.4786   data arrival time
-------------------------------------------------------------------------------------
                                       -0.1325   slack (VIOLATED)

The same run: capture at the leaf, but through mux2_1.

CTS builds through the gate

Yosys can turn flops that share an enable into enable-less flops behind one ICG (clockgate). On the MAC all 52 flops share en, so one dlclkp_1 gates them all and the enable logic in front of every flop disappears: 354 cells.

LayoutThe gated MAC after CTSThe clock port drives the ICG only; the tree hangs on its gated clock.

Tap cells
Logic
Buffers and inverters
Flip-flops
Clock gates
Clock tree
Clock nets
I/O pins

Stage: Clock tree
Cell area: 3,965.1 µm²
Utilization: 43.1 %
Wirelength (HPWL): 5,990 µm
Worst max slack: 0.2141 ns
Total negative max slack: 0.0000 ns
Worst min slack: 0.4734 ns
Clock skew: 0.0100 ns

Detailed placement
Placed: the ICG sits among the cells like any other.
A tree behind the ICG
CTS skips the net from the port, which has one sink, and builds on GCLK. The flops see the edge at 0.4650 to 0.4752 ns, ICG delay included.

Read the layout as text

mac: die 106.68 × 106.68 µm, core 96.60 × 95.20 µm, 35 rows of 2.72 µm, 39 signal pins.

Stage	Cell area	Utilization	Wirelength (HPWL)	Worst max slack	Worst min slack	Clock skew	Overflow	Cells placed
Floorplan	3,877.5 µm²	42.2 %	—	0.7232 ns	0.4253 ns	—	—	111 tap cells; I/O pins not placed yet
Global placement	3,877.5 µm²	42.2 %	4,622 µm	0.2617 ns	0.4523 ns	—	0.0986	111 tap cells, 290 logic, 11 buffers and inverters, 1 clock gates, 52 flip-flops
Detailed placement	3,877.5 µm²	42.2 %	5,590 µm	0.2339 ns	0.4589 ns	—	—	111 tap cells, 290 logic, 11 buffers and inverters, 1 clock gates, 52 flip-flops
Clock tree	3,965.1 µm²	43.1 %	5,990 µm	0.2141 ns	0.4734 ns	0.0100 ns	—	111 tap cells, 290 logic, 11 buffers and inverters, 1 clock gates, 52 flip-flops, 8 clock tree

OpenROAD 26Q2 on sky130hd, the bundled gated MAC (mac8g).

The ICG's own delay is part of every gated flop's latency. Paths between gated and ungated flops must meet their skew budgets; the ICG adds latency on only the gated branch.

Now time en, arriving 2.0 ns after the edge at an outside flop. In the gated MAC it reaches GATE at 2.0005 ns, checked at 0.0007 ns of latency: slack 2.8745 ns. In the plain MAC it passes the enable logic to a flop's D at 2.8942 ns, checked at 0.3067 ns: slack 2.3091 ns.

Timing pathen into the MAC's ICG

en → _603_setup check, latest arrival0 cells

Clock latency
Cell delay
Wire delay
Input delay
Setup time

Straight in
No logic: en arrives at 2.0005 ns.
At the root
The ICG is ahead of the buffered subtree: capture latency 0.0007 ns.
Met
Slack 2.8745 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns. Capture: clk rise edge at 5.0000 ns, latency 0.0007 ns, library setup time −0.1257 ns.

Arrival 2.0005 ns, required 4.8750 ns, slack 2.8745 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
	`en` → `_603_/GATE`	wire en	fall	0.0005	2.0005	0.0011

The report

Startpoint: en (input port clocked by clk)
Endpoint: _603_ (rising clock gating-check end-point clocked by clk)
Path Group: enable
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (propagated)
                              2.0000    2.0000 v input external delay
     1    0.0142    0.0000    0.0000    2.0000 v en (in)
                                                 en (net)
                    0.0011    0.0005    2.0005 v _603_/GATE (sky130_fd_sc_hd__dlclkp_1)
                                        2.0005   data arrival time

                              5.0000    5.0000   clock clk (rise edge)
                              0.0000    5.0000   clock source latency
     1    0.0167    0.0000    0.0000    5.0000 ^ clk (in)
                                                 clk (net)
                    0.0014    0.0007    5.0007 ^ _603_/CLK (sky130_fd_sc_hd__dlclkp_1)
                              0.0000    5.0007   clock reconvergence pessimism
                             -0.1257    4.8750   library setup time
                                        4.8750   data required time
-------------------------------------------------------------------------------------
                                        4.8750   data required time
                                       -2.0005   data arrival time
-------------------------------------------------------------------------------------
                                        2.8745   slack (MET)

OpenROAD 26Q2 flow to CTS on mac8g, 5 ns clock.

The same input on the MAC with enable muxes

Timing pathen into the plain MAC

en → _827_setup check, latest arrival4 cells

Clock latency
Cell delay
Wire delay
Input delay
Setup time

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns. Capture: clk rise edge at 5.0000 ns, latency 0.3067 ns, library setup time −0.1034 ns.

Arrival 2.8942 ns, required 5.2034 ns, slack 2.3091 ns (met).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
	`en` → `_738_/B1`	wire en	rise	0.0150	2.0150	0.0299
1	`_738_/B1` → `_738_/Y`	o21ai_0	fall	0.0914	2.1064	0.0923
	`_738_/Y` → `_740_/B1`	wire _103_	fall	0.0001	2.1065	0.0923
2	`_740_/B1` → `_740_/Y`	a211oi_1	rise	0.4809	2.5874	0.5177
	`_740_/Y` → `_742_/C`	wire _105_	rise	0.0003	2.5876	0.5177
3	`_742_/C` → `_742_/Y`	nand3_1	fall	0.1592	2.7468	0.1136
	`_742_/Y` → `_748_/B`	wire _107_	fall	0.0001	2.7469	0.1136
4	`_748_/B` → `_748_/Y`	xnor2_1	fall	0.1473	2.8942	0.0460
	`_748_/Y` → `_827_/D`	wire _048_	fall	0.0001	2.8942	0.0460

The report

Startpoint: en (input port clocked by clk)
Endpoint: _827_ (rising edge-triggered flip-flop clocked by clk)
Path Group: enable
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                              0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (propagated)
                              2.0000    2.0000 ^ input external delay
    69    0.2810    0.0000    0.0000    2.0000 ^ en (in)
                                                 en (net)
                    0.0299    0.0150    2.0150 ^ _738_/B1 (sky130_fd_sc_hd__o21ai_0)
     2    0.0054    0.0923    0.0914    2.1064 v _738_/Y (sky130_fd_sc_hd__o21ai_0)
                                                 _103_ (net)
                    0.0923    0.0001    2.1065 v _740_/B1 (sky130_fd_sc_hd__a211oi_1)
     4    0.0149    0.5177    0.4809    2.5874 ^ _740_/Y (sky130_fd_sc_hd__a211oi_1)
                                                 _105_ (net)
                    0.5177    0.0003    2.5876 ^ _742_/C (sky130_fd_sc_hd__nand3_1)
     1    0.0048    0.1136    0.1592    2.7468 v _742_/Y (sky130_fd_sc_hd__nand3_1)
                                                 _107_ (net)
                    0.1136    0.0001    2.7469 v _748_/B (sky130_fd_sc_hd__xnor2_1)
     1    0.0029    0.0460    0.1473    2.8942 v _748_/Y (sky130_fd_sc_hd__xnor2_1)
                                                 _048_ (net)
                    0.0460    0.0001    2.8942 v _827_/D (sky130_fd_sc_hd__dfrtp_1)
                                        2.8942   data arrival time

                              5.0000    5.0000   clock clk (rise edge)
                              0.0000    5.0000   clock source latency
     1    0.0254    0.0000    0.0000    5.0000 ^ clk (in)
                                                 clk (net)
                    0.0004    0.0002    5.0002 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_8)
     4    0.0309    0.0676    0.1297    5.1299 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_8)
                                                 clknet_0_clk (net)
                    0.0676    0.0006    5.1305 ^ clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_8)
    14    0.0481    0.0945    0.1744    5.3050 ^ clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_8)
                                                 clknet_2_2__leaf_clk (net)
                    0.0946    0.0018    5.3067 ^ _827_/CLK (sky130_fd_sc_hd__dfrtp_1)
                              0.0000    5.3067   clock reconvergence pessimism
                             -0.1034    5.2034   library setup time
                                        5.2034   data required time
-------------------------------------------------------------------------------------
                                        5.2034   data required time
                                       -2.8942   data arrival time
-------------------------------------------------------------------------------------
                                        2.3091   slack (MET)

The bundled mac8, the same SDC and flow.

The gate's check came 0.3060 ns earlier, but the enable lost its logic, so here gating wins. When the enable is computed by logic from flops at the leaves, as in gtree, the earlier edge is all cost. That is why clock gating enables are often critical. It is also why the ICG's place in the tree is a timing choice.

Asked in interviews

How does an integrated clock gate work?
A latch, open while the clock is low, holds the enable; an AND with the clock makes the gated clock. The enable can only change the output between pulses, so the gated clock has whole pulses or none.
What is a clock gating check?
The setup and hold check of the enable against the clock edge at the gate's clock pin. In the library it is an ordinary setup_rising/hold_rising arc on GATE.
Why are clock gating enable paths often critical?
If the enable launches on a later clock branch, the gate captures against an earlier edge. That negative skew takes time from the enable path.
How does CTS handle clock gates?
It treats the gate as part of the tree. The gated clock is a clock net with its own subtree, and the gate's delay adds to those sinks' latency. Check timing between gated and ungated sinks; their latencies need not be identical.

Try it

This is gtree. Run it: the worst setup slack, -0.1466 ns, is the enable into icg_root. Open Paths and compare the three enable endpoints.

Move icg_root down the tree: connect its CLK to u1 instead of cr, then to u2, and watch the slack and the gated flops' latency. Then try sky130_fd_sc_hd__sdlclkp_1 with SCE on a constant input port.

STAOpenSTA in OpenROAD 26Q2 · sky130hd tt_025C_1v80 Liberty · simulator service

Edit the constraints or the netlist, then run

Expected: WNS -0.1466 ns

Check yourself

Predict the outputgtree at a 1.2 ns period instead of 1.0 ns. What worst setup slack (WNS) does OpenSTA report, in ns?

create_clock -name clk -period 1.2 [get_ports clk]
set_propagated_clock [all_clocks]
set_input_transition 0.1 [get_ports clk]
group_path -name gateRoot -to [get_pins icg_root/GATE]
group_path -name gateLeaf -to [get_pins icg_leaf/GATE]
group_path -name mux -to [get_pins mf/D]

Read the netlist: design.v

module gtree (clk, d, e0, qa, qb, qm);
  input clk;
  input d;
  input e0;
  output qa;
  output qb;
  output qm;
  wire cr, ga, ga1, ga2, ga3, gb, gb1, u1, u2, u3, eq, n1, n2, n3, en, dm, qa0, qb0;
  sky130_fd_sc_hd__clkbuf_4 root (.A(clk), .X(cr));
  sky130_fd_sc_hd__dlclkp_1 icg_root (.CLK(cr), .GATE(en), .GCLK(ga));
  sky130_fd_sc_hd__clkbuf_4 ba1 (.A(ga), .X(ga1));
  sky130_fd_sc_hd__clkbuf_1 ba2 (.A(ga1), .X(ga2));
  sky130_fd_sc_hd__clkbuf_1 ba3 (.A(ga2), .X(ga3));
  sky130_fd_sc_hd__clkbuf_4 ub1 (.A(cr), .X(u1));
  sky130_fd_sc_hd__clkbuf_1 ub2 (.A(u1), .X(u2));
  sky130_fd_sc_hd__clkbuf_1 ub3 (.A(u2), .X(u3));
  sky130_fd_sc_hd__dlclkp_1 icg_leaf (.CLK(u2), .GATE(en), .GCLK(gb));
  sky130_fd_sc_hd__clkbuf_1 bb1 (.A(gb), .X(gb1));
  sky130_fd_sc_hd__dfxtp_1 ef (.CLK(u3), .D(e0), .Q(eq));
  sky130_fd_sc_hd__inv_1 e1 (.A(eq), .Y(n1));
  sky130_fd_sc_hd__nand2_1 e2 (.A(n1), .B(d), .Y(n2));
  sky130_fd_sc_hd__nor2_1 e3 (.A(n2), .B(eq), .Y(n3));
  sky130_fd_sc_hd__xor2_1 e4 (.A(n3), .B(d), .X(en));
  sky130_fd_sc_hd__dfxtp_1 fa0 (.CLK(ga3), .D(d), .Q(qa0));
  sky130_fd_sc_hd__dfxtp_1 fa1 (.CLK(ga3), .D(qa0), .Q(qa));
  sky130_fd_sc_hd__dfxtp_1 fb0 (.CLK(gb1), .D(d), .Q(qb0));
  sky130_fd_sc_hd__dfxtp_1 fb1 (.CLK(gb1), .D(qb0), .Q(qb));
  sky130_fd_sc_hd__mux2_1 mx (.A0(qm), .A1(d), .S(en), .X(dm));
  sky130_fd_sc_hd__dfxtp_1 mf (.CLK(u3), .D(dm), .Q(qm));
endmodule

ConceptAn enable launched at a leaf flop goes to an ICG whose CLK pin is two buffers nearer the root. What does that do to the enable's setup check?

It gains time, since the ICG's edge arrives earlierNothing: the clock gating check has no setup, only holdIt loses about two buffer delays: the capture edge is earlierIt loses the ICG's own delay, CLK to GCLK, from its setup

ConceptWhy might you place an ICG near the clock root despite the tighter enable timing?

CTS can only build a tree behind an ICG placed at the rootIt removes the clock gating check, which only leaf ICGs haveIts gated flops get less latency than any ungated flopIt stops more of the tree when the enable is low, saving more power

ConceptWhat is the SCE pin of sdlclkp_1 for?

In test it forces the gated clock on so scan can shiftIt slows GCLK for hold, like a built-in delay cellIt resets the latch so the gated clock starts lowIt selects which edge of CLK the cell gates

ConceptAfter CTS on the gated MAC, the flops see the clock at about 0.47 ns. A second block of ungated flops gets its own tree straight from the port. What must CTS take care of?

Removing the ICG from the tree, since STA cannot time through itBalancing both groups, since the ICG delay is skew between themRaising the clock uncertainty by the ICG's delay for every pathNothing: gated and ungated flops never share timing paths

Remember

sky130's dlclkp_1 is a latch and an AND in one cell, with a setup and hold check on GATE against CLK: the clock gating check.
An ICG is upstream of its gated sinks; an enable launched on a later clock branch sees negative skew at the gate.
An ICG near the root saves more clock power and leaves the enable less time; one near the leaves is easier to time.
CTS builds the tree on the gated clock, the ICG's delay adds to the gated flops' latency, and paths crossing between gated and ungated sinks must meet setup and hold.