Widths, truncation and sign

How SystemVerilog sizes an expression

Before it adds, SystemVerilog picks one width for the whole expression. For +, -, * and the bitwise operators, that width is the widest operand or the target of the assignment, whichever is larger. The operands are extended to that width, the operation runs, and the result is cut to fit the target. Dropping the upper bits is called truncation.

In sum <= sum + d every name is 8 bits wide, so the addition runs at 8 bits. Its carry, bit 8, is computed by nobody and stored nowhere. Give sum nine bits and the same line adds at 9 bits: the target is now the widest thing in the statement.

Not every operator follows the context. Some size each operand alone, by its own width: these operands are self-determined. The braces of a concatenation are the trap here. A comparison is a small context of its own: its two sides are sized to the wider side, and the result is a single bit.

When an expression is signed

Signedness follows a stricter rule than width. An expression is signed only if every operand in it is signed. One unsigned operand makes the whole expression unsigned, and a signed -1 is then read as its bit pattern, 1111_1111, which is 255. The target of the assignment does not count.

Unsigned operands hide in ordinary code. A port declared without signed is unsigned. A literal with a base, such as 8'd1, is unsigned unless it carries an s, as in 8'sd1. A part-select such as x[7:0] and a concatenation are unsigned even when every bit comes from a signed variable. A plain decimal number such as 1 is signed and 32 bits wide.

input logic signed [7:0] x,
input logic        [7:0] thr,
...
assign low = x < thr;  // unsigned

input logic signed [7:0] x,
input logic signed [7:0] thr,
...
assign low = x < thr;  // signed

Signedness changes which function the gates compute, and not how many there are. Measured on this flow, an 8-bit compare x < thr is 29 cells either way: 9 levels of logic unsigned, 10 signed. In the lab design, making the threshold signed leaves the count at 71 cells.

What Lint reports, and the lab

Lint flags a statement whose two sides have different widths. Write s8 = {1'b0, a} + b; and Verilator 5.052 reports %Warning-WIDTHTRUNC: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's ADD generates 9 bits. Write s9 = {a + b}; and it reports WIDTHEXPAND.

The lab design draws no width or sign warning at all. Every name in sum <= sum + d is 8 bits, so the sides match, and a signed-against-unsigned compare is legal code. Lint compares the code with itself. Only the brief says the total must reach 300 and the reading can be negative.

Run the lab: the total reads 44 and the bench marks two wrong flags. Press Synthesize: 71 cells, 8 flops, 14 levels of logic on this flow. Now give sum nine bits, with its reset value, and declare thr as signed. Run again: the total is 300 and no flag is wrong. Synthesize: 77 cells, 9 flops, 16 levels. The carry cost one flop, five gates and two levels; the sign cost nothing.

Try it

Edges 0 and 1 are reset. At edge 2 the total takes 200. At edge 3 it should be 300 and reads 44: the carry fell off bit 7. In the same line, -1 against a threshold of 1 gives low = 0, because the unsigned thr makes the compare unsigned. -128 at edge 5 is missed the same way.

Change the sum port to [8:0] and its reset value to 9'd0, and declare thr as logic signed [7:0]. The bench then prints a total of 300 and 0 wrong flags. Synthesize before and after: 71 cells, 8 flops and 14 levels become 77 cells, 9 flops and 16 levels.

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic        [7:0] d = 0;
  logic        [8:0] sum;                 // 9 bits: wide enough for the fixed design too
  logic signed [7:0] x = 0, thr = 0;
  logic              low;
  int wrong_low = 0;
  acc dut (.clk(clk), .rst_n(rst_n), .d(d), .sum(sum), .x(x), .thr(thr), .low(low));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    if (low !== (x < thr)) wrong_low++;      // the bench compares as signed numbers
    $display("e%0d d=%0d sum=%0d x=%0d thr=%0d low=%b%s", edge_n, d, sum, x, thr, low, low === (x < thr) ? "" : "  wrong");
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    d = 200; x = 5;  thr = 1; tick();
    d = 100; x = -1;          tick();
    d = 0;   x = 1;           tick();
    x = -128;                 tick();
    $display("total %0d, want 300; %0d low flags wrong", sum, wrong_low);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

Check yourself

module tb;
  logic [3:0] a = 4'd12, b = 4'd7;
  logic [3:0] s;
  initial begin
    s = a + b;
    $display("s=%0d", s);
    $finish(0);
  end
endmodule

low = x < $signed(tu);

low = x < 1;

low = x < ts;

low = x < 8'd1;