Parameters, generate and $clog2

One number, every width derived from it

A parameter is a constant with a name, which each instance of a module may set: adder_tree #(.N(8)) u8 (...). A localparam is a constant computed inside the module that no instance can override. Write each free choice once, as a parameter, and derive everything else from it.

$clog2(x) returns the base-2 logarithm of x, rounded up. N inputs of W bits sum to at most N times (2^W - 1), which needs W + $clog2(N) bits. Four inputs of 8 bits need 10 bits; eight need 11.

logic [W+1:0] s;   // W bits and two carry bits

localparam int OW = W + $clog2(N);
logic [OW-1:0] s;

A generate loop builds copies

A for loop with a genvar outside any process is a generate loop. The tool runs it at elaboration. Each pass creates one block with its own name: g_node[0], g_node[1], and so on. Each block has its own signal s, named g_node[3].s, so the blocks can refer to one another.

Refuse a bad parameter, and leave macros behind

Some parameter values make no sense. With N = 1 there is nothing to add. A generate if with $error inside reports the value at elaboration. The tools do not agree on what happens next, so the legal range belongs in the brief too.

Older code uses a macro for the same job, a name defined with the define compiler directive. A macro is text substitution with no scope. It applies to every file compiled after it, until something redefines it. Which value a block sees depends on the compile order. A parameter belongs to one instance. Use parameters, and localparam for every derived value.

The lab ships the adder tree as the team wrote it. Run it: the N = 4 copy is right in all five cycles, the N = 8 copy is wrong twice. Change logic [W+1:0] s; to logic [OW-1:0] s; and run again: zero wrong sums. Synthesize gives 119 cells. Then change the default N = 4 to 8, as an instance would: 281 cells, 25 levels.

Try it

The N = 4 copy is right in every cycle, and so is the N = 8 copy until its true sum passes 1023. Then 1740 prints as 716 and 2040 as 1016: the partial sums hold 10 bits, and the 1024 bit falls off at the root.

Change the width of s to [OW-1:0] and run again: every line matches its model and the summary reads 0 wrong sums twice. The design at its default N = 4 synthesizes to the same 119 cells either way, because there W + 2 and OW are both 10.

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic [3:0][7:0] in4;                   // N = 4, W = 8
  logic [7:0][7:0] in8;                   // N = 8, W = 8
  logic [9:0]      sum4;                  // 8 + $clog2(4) = 10 bits
  logic [10:0]     sum8;                  // 8 + $clog2(8) = 11 bits
  int want4, want8, wrong4 = 0, wrong8 = 0;
  // Input j of both copies gets base + step * j; the model adds them up.
  task automatic fill(input int base, input int step);
    want4 = 0; want8 = 0;
    for (int j = 0; j < 4; j++) begin in4[j] = 8'(base + step * j); want4 += in4[j]; end
    for (int j = 0; j < 8; j++) begin in8[j] = 8'(base + step * j); want8 += in8[j]; end
  endtask
  adder_tree #(.N(4), .W(8)) u4 (.in(in4), .sum(sum4));
  adder_tree #(.N(8), .W(8)) u8 (.in(in8), .sum(sum8));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    if (sum4 != want4) wrong4++;
    if (sum8 != want8) wrong8++;
    $display("e%0d N=4: %0d (want %0d)  N=8: %0d (want %0d)%s", edge_n, sum4, want4, sum8, want8,
             (sum4 == want4 && sum8 == want8) ? "" : "  wrong");
  endtask
  initial begin
    fill(1, 0);   tick();                 // every input 1
    fill(10, 10); tick();                 // 10, 20, 30, ...
    fill(100, 0); tick();                 // every input 100
    fill(200, 5); tick();                 // 200, 205, 210, ...
    fill(255, 0); tick();                 // every input at its largest value
    $display("N=4: %0d wrong sums, N=8: %0d wrong sums", wrong4, wrong8);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

Check yourself

module ptr #(parameter int DEPTH = 8) (output int bits);
  localparam int AW = $clog2(DEPTH);   // address width for DEPTH entries
  logic [AW-1:0] addr;
  assign bits = $bits(addr);
endmodule
module tb;
  int a, b, c;
  ptr #(.DEPTH(5)) p5 (.bits(a));
  ptr #(.DEPTH(8)) p8 (.bits(b));
  ptr #(.DEPTH(9)) p9 (.bits(c));
  initial begin
    #1 $display("%0d %0d %0d", a, b, c);
    $finish(0);
  end
endmodule

y = (x == 8'hff);

y = (x == (2**W) - 1);

y = (x == '1);

y = (x == {W{1'b1}});

y = &x;