Moore, Mealy and when the output changes

Where the output comes from

A finite state machine (FSM) is a state register, a next-state function and an output function. In a Moore machine the outputs depend on the state alone, so they change only when the state does: at a clock edge. In a Mealy machine the outputs depend on the state and the current inputs, so they also change whenever an input changes.

What the gates and the timing say

Moore costs a cycle of latency here, and Mealy costs a clean output. A third choice, the registered Mealy output, computes the Mealy value and stores it in a flop: one cycle late like Moore, and steady for the whole cycle.

The cell counts are equal because this machine is tiny. The difference is where ack comes from. In the Moore version it is the output of a flop. In the Mealy version it is an AND gate fed by req, so any change of req, early, late or a glitch, reaches ack.

The rule this track follows: an output that leaves the module is Moore or registered, so the next block sees a value that changes only at the edge. A Mealy output is fine inside a module, where the logic that reads it is timed with it.

Converting Mealy to Moore

1. Find the input in the output equation

   Here ack reads req. That input is what makes the output Mealy.

2. Move it into the next state

   The arc READY to DONE already fires on req, so DONE means "req was seen". Some machines need a new state for this.

3. Decode the output from the state

   ack = (st_q == DONE). The output now waits for the edge, one cycle later, and is steady for the whole cycle.

Run the lab: three requests, no waiting, and the two lines that say ack moved 1 ns and 3 ns after the edge. Then change the assign to ack = (st_q == DONE) and run again. Each ack now comes one cycle later, the notes about moving inside the cycle are gone, and the summary counts 3 cycles of waiting. Synthesize both: 2 cells each.

Try it

Each line shows a cycle as the receiver will sample it at the next edge. Three times ack rose inside the cycle, as late as req did: 1 ns, 3 ns and 1 ns after the edge. Each handshake took one edge and no request waited.

Change the assign to ack = (st_q == DONE) and run: ack is 1 in cycles e4, e7 and e10, never moves inside a cycle, and the summary reads 3 cycles waiting for ack. The bench file prints the state through dut.st_q, so keep the state names.

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic req = 0;
  logic ack;
  int   served = 0, waited = 0;
  time  t_edge = 0, t_ack = 0;
  always @(ack) t_ack = $time;           // when ack last moved
  // One line per cycle, printed 9 ns after edge k: the values the receiver samples at edge k+1.
  always @(posedge clk) begin
    t_edge = $time;
    #9 if (edge_n >= 2) begin
      if (t_ack > t_edge)
        $display("e%0d st=%s req=%b ack=%b  (ack moved %0d ns after the edge)", edge_n, dut.st_q ? "DONE " : "READY", req, ack, t_ack - t_edge);
      else
        $display("e%0d st=%s req=%b ack=%b", edge_n, dut.st_q ? "DONE " : "READY", req, ack);
    end
  end
  // Raise req `at` ns after the next edge; hold it until ack is 1 at an edge.
  task automatic request(input int at);
    @(posedge clk); #(at) req = 1;
    @(posedge clk);
    while (ack !== 1'b1) begin           // not yet: wait one more edge
      waited++;
      @(posedge clk);
    end                                  // this edge is the handshake
    served++;
    #1 req = 0;
  endtask
  req_ack dut (.clk(clk), .rst_n(rst_n), .req(req), .ack(ack));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    @(posedge clk);                       // cycle 2: idle
    request(1);                           // req rises 1 ns after edge 3
    request(3);                           // a late req: 3 ns after the edge
    request(1);
    repeat (2) @(posedge clk); #9.5;
    $display("%0d requests, %0d cycles waiting for ack", served, waited);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

Check yourself

// req_ack: acknowledges each request once, then takes one cycle (DONE) before the next.
// The requester holds req until it sees ack = 1 at a rising edge.
module req_ack (
  input  logic clk,
  input  logic rst_n,      // asynchronous, active-low
  input  logic req,
  output logic ack
);
  typedef enum logic {READY, DONE} state_e;
  state_e st_q, st_d;

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) st_q <= READY;
    else        st_q <= st_d;

  always_comb begin
    st_d = st_q;
    unique case (st_q)
      READY:   if (req) st_d = DONE;
      DONE:    st_d = READY;
      default: st_d = READY;
    endcase
  end

  // Moore: ack depends on the state only.
  assign ack = (st_q == DONE);
endmodule

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic req = 0;
  logic ack;
  req_ack dut (.clk(clk), .rst_n(rst_n), .req(req), .ack(ack));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    repeat (3) @(posedge clk);
    #1 req = 1;                          // req rises 1 ns after edge 4
    @(posedge clk);
    while (ack !== 1'b1) @(posedge clk); // the requester samples ack at each edge
    #1 $display("ack seen at edge e%0d", edge_n);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) ack <= 1'b0;
    else        ack <= (st_q == READY) && req;

assign ack = (st_q == READY) && req;

assign ack = (st_q != READY);

assign ack = (st_q == DONE);