Handshakes as FSMs

// A source and a sink joined by a valid/ready link. On go, the source sends four beats
// (data 1, 2, 3, 4). The sink holds one beat until its consumer takes it (take = 1).

// src: offers a beat while it is in SEND; the beat moves at an edge where valid and ready are 1.
module src (
  input  logic       clk,
  input  logic       rst_n,
  input  logic       go,
  input  logic       ready,
  output logic       valid,
  output logic [7:0] data
);
  typedef enum logic {IDLE, SEND} state_e;
  state_e     st_q, st_d;
  logic [1:0] n_q;                          // beats already sent

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin
      st_q <= IDLE; n_q <= '0;
    end else begin
      st_q <= st_d;
      if (valid && ready) n_q <= n_q + 2'd1;
    end

  always_comb begin
    st_d = st_q;
    unique case (st_q)
      IDLE:    if (go) st_d = SEND;
      SEND:    if (valid && ready && n_q == 2'd3) st_d = IDLE;
      default: st_d = IDLE;
    endcase
  end

  assign valid = (st_q == SEND);            // from the state only
  assign data  = 8'(n_q) + 8'd1;
endmodule

// snk: a one-beat buffer. ready says "I have room"; take empties it.
module snk (
  input  logic       clk,
  input  logic       rst_n,
  input  logic       valid,
  input  logic [7:0] data,
  input  logic       take,
  output logic       ready,
  output logic [7:0] got
);
  typedef enum logic {EMPTY, FULL} state_e;
  state_e st_q, st_d;

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin
      st_q <= EMPTY; got <= '0;
    end else begin
      st_q <= st_d;
      if (valid && ready) got <= data;
    end

  always_comb begin
    st_d = st_q;
    unique case (st_q)
      EMPTY:   if (valid && ready) st_d = FULL;
      FULL:    if (take) st_d = EMPTY;
      default: st_d = EMPTY;
    endcase
  end

  assign ready = (st_q == EMPTY);           // from the state only
endmodule

module link (
  input  logic       clk,
  input  logic       rst_n,
  input  logic       go,
  input  logic       take,
  output logic       valid,
  output logic       ready,
  output logic [7:0] data,
  output logic [7:0] got
);
  src u_src (.clk(clk), .rst_n(rst_n), .go(go), .ready(ready), .valid(valid), .data(data));
  snk u_snk (.clk(clk), .rst_n(rst_n), .valid(valid), .data(data), .take(take), .ready(ready), .got(got));
endmodule

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic       go = 0, take = 0;           // the consumer sleeps at first
  logic       valid, ready;
  logic [7:0] data, got;
  int         beats = 0, last_beat = 0;
  link dut (.clk(clk), .rst_n(rst_n), .go(go), .take(take), .valid(valid), .ready(ready), .data(data), .got(got));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    if (valid && ready) begin beats++; last_beat = edge_n + 1; end   // this beat moves at the next edge
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    go = 1; tick(); go = 0;                 // go is sampled at edge 2
    repeat (3) tick();                      // edges 3 to 5: take is 0
    take = 1;                               // from 1 ns after edge 5, take every beat
    repeat (8) tick();
    $display("%0d beats, the last at e%0d", beats, last_beat);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule