Capstone: a UART transmitter

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  localparam int CPB = 4;                 // clock cycles per bit, for the transmitter and the decoder
  logic       in_valid = 0;
  logic [7:0] in_data = 0;
  logic       in_ready, txd;
  // Offer one byte and hold it until the transmitter takes it at an edge where in_ready is 1.
  task automatic send(input logic [7:0] b);
    in_valid = 1; in_data = b;
    while (!in_ready) tick();
    tick();                               // the edge that accepts the byte
    in_valid = 0;
  endtask
  // Wait until the transmitter is free, then leave the line idle for two bit-times.
  task automatic pause();
    while (!in_ready) tick();
    repeat (2 * CPB) tick();
  endtask
  uart_tx #(.CLKS_PER_BIT(CPB)) dut (.*);
  serial_decoder #(.CLKS_PER_BIT(CPB)) dec (.clk(clk), .line(txd));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    send(8'h80); pause();
    send(8'h5a); pause();
    send(8'hc3); pause();
    send(8'h31); send(8'h62);             // back to back: the second waits for in_ready
    pause();
    repeat (12 * CPB) tick();             // let the decoder finish the last frame
    $display("%0d frames, %0d errors", dec.frames, dec.errors);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

// serial_decoder.sv: the receiving end of the bench (read-only).
`timescale 1ns/1ps
// It samples the line once per cycle, 1 ns after each rising edge. When the line falls, the start
// bit has begun; the decoder waits half a bit-time to reach its middle, then samples every
// CLKS_PER_BIT cycles: eight data bits (least significant first), the parity bit, the stop bit.
// It prints one line per frame: the edge where the start bit began, the byte, and a verdict:
//   e3 rx 0x5a ok        e3 rx 0x5a PARITY ERROR        e3 rx 0x5a FRAME ERROR (stop bit 0)
module serial_decoder #(parameter int CLKS_PER_BIT = 4) (input logic clk, input logic line);
  int e = -1;                                    // the number of the last rising edge
  always @(posedge clk) e = e + 1;
  int frames = 0, errors = 0;
  task automatic skip(input int n);              // move n samples on
    repeat (n) begin @(posedge clk); #1; end
  endtask
  initial begin : rx
    logic prev, stop, par;
    logic [7:0] b;
    int s;
    prev = 1'b1;
    forever begin
      skip(1);
      if (prev === 1'b1 && line === 1'b0) begin  // the first low sample of a start bit
        s = e;
        skip(CLKS_PER_BIT / 2);                  // the middle of the start bit
        if (line === 1'b0) begin
          for (int k = 0; k < 8; k++) begin skip(CLKS_PER_BIT); b[k] = line; end
          skip(CLKS_PER_BIT); par  = line;
          skip(CLKS_PER_BIT); stop = line;
          frames++;
          if (stop !== 1'b1)            begin errors++; $display("e%0d rx 0x%h FRAME ERROR", s, b); end
          else if ((^b ^ par) !== 1'b0) begin errors++; $display("e%0d rx 0x%h PARITY ERROR", s, b); end
          else                                         $display("e%0d rx 0x%h ok", s, b);
        end
      end
      prev = line;
    end
  end
endmodule