Sequence detectors and overlap

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic din = 0;
  logic match;
  bit   show = 0;                         // print one line per edge
  logic [3:0] win = 0;                    // the model: the last four bits fed
  int   nd = 0, nm = 0;                   // matches counted: design, model
  // Feed one bit: drive it after an edge, let the next edge sample it, count both answers.
  task automatic feed(input logic b);
    din = b; tick();
    win = {win[2:0], b};
    nd += match;
    nm += (win == 4'b1011);
  endtask
  // Feed the n low bits of v, leftmost first, so 7'b1011011 arrives as 1, 0, 1, 1, 0, 1, 1.
  task automatic feed_bits(input logic [63:0] v, input int n);
    for (int i = n - 1; i >= 0; i--) feed(v[i]);
  endtask
  det1011 dut (.*);                       // ports connect to the signals of the same name
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    if (show && rst_n) $display("e%0d din=%b match=%b", edge_n, din, match);
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    feed_bits(11'b10110111011, 11);
    $display("matches=%0d", nd);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule
// det1011: match is 1 for one cycle after the input stream ends in 1011.
// One input bit per clock edge. Matches may overlap: 1011011 holds two.
module det1011 (
  input  logic clk,
  input  logic rst_n,      // active-low, asynchronous
  input  logic din,
  output logic match
);
  // Each state names the part of 1011 seen so far.
  typedef enum logic [1:0] {S0, S1, S10, S101} state_e;
  state_e st_q, st_d;

  always_comb begin
    st_d = st_q;
    unique case (st_q)
      S0:      if (din) st_d = S1;   else st_d = S0;
      S1:      if (din) st_d = S1;   else st_d = S10;
      S10:     if (din) st_d = S101; else st_d = S0;
      S101:    if (din) st_d = S1;   else st_d = S10;    // keep the tail: "1" or "10"
      default: st_d = S0;
    endcase
  end

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin
      st_q  <= S0;
      match <= 1'b0;
    end else begin
      st_q  <= st_d;
      match <= (st_q == S101) && din;                     // 1011 just completed
    end
endmodule