The two-flop synchronizer and what it cannot carry

Why the bits land in different cycles

In silicon, the four bit wires never arrive at exactly the same instant: wires differ in length and load. The lab bench models that by giving each bit wire its own delay, 0.4, 1.2, 2.8 and 2.0 ns. No metastability model is needed. Simulator note: zero-delay RTL never shows metastability, and the four wire delays are a model of skew, not measured silicon.

A two-flop synchronizer gives a bit a clean value and a known timing in the new clock. It cannot say in which receiving cycle the change lands. For one bit that does not matter. For several bits it means each may land in a different cycle, and the receiver reads a mixture of old and new: a torn value.

What may cross a two-flop synchronizer

1. One bit per synchronizer

   Never put two bits that change together through separate synchronizers and use them as one value.

2. No logic between the two flops

   Logic there eats the settle time of the first flop, which is the whole point of the second.

3. Send from a flop

   Drive the crossing wire straight from a flop in its own domain. Logic there can glitch, and every glitch is another chance to be caught mid-change.

4. Name the synchronizer

   Put the flops in one module, such as sync2, so reviewers and CDC tools can find every crossing.

Gray code: one bit per step

A Gray code orders the numbers so that each step changes exactly one bit. Binary to Gray is g = b ^ (b >> 1). Gray back to binary takes, for each bit i, the XOR of Gray bits i and above.

assign count_x = cnt;

logic [3:0] cnt, cnt_d, gray;
assign cnt_d = cnt + 4'd1;
always_ff @(posedge clk_a or negedge rst_n)
  if (!rst_n) begin cnt <= 4'd0; gray <= 4'd0; end
  else        begin cnt <= cnt_d; gray <= cnt_d ^ (cnt_d >> 1); end
assign count_x = gray;               // one bit changes per step

The Gray value is computed from cnt_d, the next count, and registered, so the wires change once per step from a flop. The receiver converts back after the synchronizers.

always_comb                          // Gray to binary: bit i is the XOR of bits 3..i
  for (int i = 0; i < 4; i++) count_q[i] = ^(s2 >> i);

Gray works for a count that steps by one through a power-of-two range. A count that jumps, or wraps at another value, changes several bits at once again.

The lab ships with binary on the wires. Run it and find the TORN line. Then replace the body of count_tx with the Gray version, and assign count_q = s2; with the decode. Run again: torn=0.

Try it

Each line is printed 1 ns after an edge of clk. rx steps by one or repeats, because clk is faster than clk_a, except at edge 12. The 15 to 0 step at edge 23 also changed four bits, but on this bench no edge fell between their arrivals.

With the Gray sender and the decode, the wires show 0100, 1100, 1101 around the same edges, and the last line reads torn=0. Synthesize both: 18 cells and 12 flops, then 29 cells and 15 flops.

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // the sampling clock: rising edges at 5, 15, 25, ... ns
  logic clk_a = 0;                      // the second clock: rising edges at 8.75, 21.75, ... ns
  initial begin
    #8.75;
    forever begin clk_a = 1; #6.5; clk_a = 0; #6.5; end
  end
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so asynchronous resets act before any clock
  int edge_n = -1;                        // the number of the last rising edge of clk
  always @(posedge clk) edge_n = edge_n + 1;
  logic [3:0] count_x;                    // the bus as count_tx drives it
  wire  [3:0] count_w;                    // the same bus at count_rx: each bit wire has its own delay
  logic [3:0] count_q;
  assign #0.4 count_w[0] = count_x[0];
  assign #1.2 count_w[1] = count_x[1];
  assign #2.8 count_w[2] = count_x[2];
  assign #2.0 count_w[3] = count_x[3];
  logic [3:0] last = 0;                   // the last value that was not torn
  int torn = 0;
  count_tx u_tx (.clk_a(clk_a), .rst_n(rst_n), .count_x(count_x));
  count_rx u_rx (.clk(clk), .rst_n(rst_n), .count_x(count_w), .count_q(count_q));
  // Advance to the next rising edge of clk, wait for the design to settle, then print.
  task automatic tick();
    @(posedge clk); #1;
    if (count_q != last && count_q != last + 4'd1) begin
      torn++;                             // a value the count never held at this point
      $display("e%0d x=%b rx=%0d TORN", edge_n, count_x, count_q);
    end
    else begin
      $display("e%0d x=%b rx=%0d", edge_n, count_x, count_q);
      last = count_q;
    end
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, clk edges 0 and 1 in reset, released 1 ns after edge 1
    repeat (24) tick();
    $display("torn=%0d", torn);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

Check yourself

module tb;
  function automatic logic [2:0] gray(input logic [2:0] b);
    return b ^ (b >> 1);
  endfunction
  initial begin
    $display("%b %b %b %b %b %b %b %b", gray(0), gray(1), gray(2), gray(3), gray(4), gray(5), gray(6), gray(7));
    $finish(0);
  end
endmodule

function automatic logic [3:0] enc(input logic [3:0] b);
  return b;
endfunction
function automatic logic [3:0] dec(input logic [3:0] g);
  return g;
endfunction

function automatic logic [3:0] enc(input logic [3:0] b);
  return {b[3], b[3] ^ b[2], b[2] ^ b[1], b[1] ^ b[0]};
endfunction
function automatic logic [3:0] dec(input logic [3:0] g);
  return {g[3], ^g[3:2], ^g[3:1], ^g[3:0]};
endfunction

function automatic logic [3:0] enc(input logic [3:0] b);
  return b ^ (b >> 1);
endfunction
function automatic logic [3:0] dec(input logic [3:0] g);
  dec[3] = g[3];
  for (int i = 2; i >= 0; i--) dec[i] = dec[i + 1] ^ g[i];
endfunction

function automatic logic [3:0] enc(input logic [3:0] b);
  return b ^ (b >> 1);
endfunction
function automatic logic [3:0] dec(input logic [3:0] g);
  for (int i = 0; i < 4; i++) dec[i] = ^(g >> i);
endfunction