Gray codes and the asynchronous FIFO

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // the sampling clock: rising edges at 5, 15, 25, ... ns
  logic wclk = 0;                      // the second clock: rising edges at 2.6, 15.6, ... ns
  initial begin
    #2.6;
    forever begin wclk = 1; #6.5; wclk = 0; #6.5; end
  end
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so asynchronous resets act before any clock
  int edge_n = -1;                        // the number of the last rising edge of clk
  always @(posedge clk) edge_n = edge_n + 1;
  localparam int N = 300;                 // words the producer sends: 0, 1, 2, ...
  logic       write_en = 0, read_en = 0, full, empty, read_valid;
  logic [7:0] write_data = 0, read_data;
  logic [3:0] read_level;
  int sent = 0, taken = 0, answers = 0, wrong = 0, over = 0, expect_q = 0, wcyc = 0;

  // Producer (write domain): offers the next number at 20 of every 32 write-clock edges.
  always @(posedge wclk) begin
    if (write_en && !full) sent++;        // a write is taken at an edge where full was 0
    wcyc++;
    #1 write_en = rst_n && sent < N && (wcyc % 32) < 20;
    write_data = sent[7:0];
  end
  // Consumer (read domain): asks for a word, except at 12 of every 40 edges.
  always @(posedge clk) begin
    if (read_en && !empty) taken++;       // a read is taken at an edge where empty was 0
    #0.5 read_en = rst_n && (edge_n % 40) < 28;
  end

  // A model of the crossing (bench only): when a pointer bit changes less than 1.5 ns before the
  // sampling edge, the first flop catches its old or its new value, picked at random from a fixed
  // seed. Real flops do this; zero-delay RTL flops never do.
  logic [3:0] w_old = 0, w_now = 0, r_old = 0, r_now = 0;
  realtime    w_t = -100, r_t = -100;
  int unsigned seed = 1;
  always @(dut.wptr_q) begin w_old = w_now; w_now = dut.wptr_q; w_t = $realtime; end
  always @(dut.rptr_q) begin r_old = r_now; r_now = dut.rptr_q; r_t = $realtime; end
  always @(posedge clk) if ($realtime - w_t < 1.5) #0.1 for (int i = 0; i < 4; i++) begin
    seed = seed * 1103515245 + 12345;
    if (seed[16]) dut.rq1_wptr[i] = w_old[i];
  end
  always @(posedge wclk) if ($realtime - r_t < 1.5) #0.1 for (int i = 0; i < 4; i++) begin
    seed = seed * 1103515245 + 12345;
    if (seed[16]) dut.wq1_rptr[i] = r_old[i];
  end

  // The checks, once per read-clock edge: the level against the words held, every answer
  // against the next number. After a wrong answer the checker follows on from it.
  task automatic check();
    if (edge_n >= 20 && edge_n <= 25)
      $display("e%0d wptr=%b seen=%b read_level=%0d holds=%0d empty=%b", edge_n, dut.wptr_q, dut.rq2_wptr, read_level, sent - taken, empty);
    if (read_level > sent - taken) begin
      over++;
      if (over <= 3) $display("e%0d the read side sees %0d words, the FIFO holds %0d", edge_n, read_level, sent - taken);
    end
    if (read_valid) begin
      answers++;
      if (read_data !== expect_q[7:0]) begin
        wrong++;
        if (wrong <= 3) $display("e%0d read %0d, expected %0d", edge_n, read_data, expect_q);
        expect_q = read_data;
      end
      expect_q++;
    end
  endtask
  afifo dut (.wclk(wclk), .wrst_n(rst_n), .write_en(write_en), .write_data(write_data), .full(full),
             .rclk(clk), .rrst_n(rst_n), .read_en(read_en), .read_valid(read_valid), .read_data(read_data),
             .empty(empty), .read_level(read_level));
  // Advance to the next rising edge of clk, wait for the design to settle, then print.
  task automatic tick();
    @(posedge clk); #1;
    check();
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, clk edges 0 and 1 in reset, released 1 ns after edge 1
    while (answers < N && edge_n < 2000) tick();
    $display("%0d words sent, %0d read back, %0d wrong; %0d edges where read_level was above the words held", sent, answers, wrong, over);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule