Pulse, toggle and handshake synchronizers

// hs_tx: the fast side of a four-phase handshake. A pulse starts a transfer when the side is free.
module hs_tx (
  input  logic       clk_f,
  input  logic       rst_n,
  input  logic       pulse_f,        // start a transfer (only when busy is 0)
  input  logic [7:0] data_f,
  input  logic       ack,            // from the clk domain
  output logic       req,            // to the clk domain
  output logic [7:0] data_x,         // held still while req is 1
  output logic       busy
);
  logic a1, a2;                      // ack, synchronized into clk_f
  always_ff @(posedge clk_f or negedge rst_n)
    if (!rst_n) begin a1 <= 1'b0; a2 <= 1'b0; end
    else        begin a1 <= ack;  a2 <= a1;   end
  always_ff @(posedge clk_f or negedge rst_n)
    if (!rst_n)                      begin req <= 1'b0; data_x <= 8'd0; end
    else if (!busy && pulse_f)       begin req <= 1'b1; data_x <= data_f; end   // 1: raise req
    else if (req && a2)              req <= 1'b0;                               // 3: ack seen, drop req
  assign busy = req | a2;            // free again once ack has dropped (4)
endmodule

// hs_rx: the slow side.
module hs_rx (
  input  logic       clk,
  input  logic       rst_n,
  input  logic       req,
  input  logic [7:0] data_x,
  output logic       ack,
  output logic       pulse_s,        // 1 for one cycle, when data_s is new
  output logic [7:0] data_s
);
  logic r1, r2;                      // req, synchronized into clk
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin r1 <= 1'b0; r2 <= 1'b0; end
    else        begin r1 <= req;  r2 <= r1;   end
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin ack <= 1'b0; pulse_s <= 1'b0; data_s <= 8'd0; end
    else begin
      pulse_s <= r2 && !ack;
      if (r2 && !ack)      begin ack <= 1'b1; data_s <= data_x; end   // 2: take the data, raise ack
      else if (!r2 && ack) ack <= 1'b0;                                // 4: req dropped, drop ack
    end
endmodule

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // the sampling clock: rising edges at 5, 15, 25, ... ns
  logic clk_f = 0;                      // the second clock: rising edges at 1.75, 4.75, ... ns
  initial begin
    #1.75;
    forever begin clk_f = 1; #1.5; clk_f = 0; #1.5; end
  end
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so asynchronous resets act before any clock
  int edge_n = -1;                        // the number of the last rising edge of clk
  always @(posedge clk) edge_n = edge_n + 1;
  logic pulse_f = 0, level, pulse_s;
  int sent = 0, seen = 0;
  task automatic pulse_after(input int gap);   // gap idle edges of clk_f, then a one-cycle pulse
    repeat (gap) @(posedge clk_f);
    #0.5 pulse_f = 1; sent++;
    @(posedge clk_f); #0.5 pulse_f = 0;
  endtask
  initial begin : sender                      // the fast domain's pulses
    @(posedge rst_n);
    pulse_after(10);
    pulse_after(10);
    pulse_after(10);
    pulse_after(10);
    pulse_after(10);
    pulse_after(8);
    pulse_after(1);
  end
  pulse_tx u_tx (.clk_f(clk_f), .rst_n(rst_n), .pulse_f(pulse_f), .level(level));
  pulse_rx u_rx (.clk(clk), .rst_n(rst_n), .level(level), .pulse_s(pulse_s));
  // Advance to the next rising edge of clk, wait for the design to settle, then print.
  task automatic tick();
    @(posedge clk); #1;
    if (pulse_s) seen++;
    $display("e%0d sent=%0d level=%b pulse_s=%b seen=%0d", edge_n, sent, level, pulse_s, seen);
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, clk edges 0 and 1 in reset, released 1 ns after edge 1
    repeat (30) tick();
    $display("sent=%0d seen=%0d", sent, seen);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule