Reset across clock domains

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // the sampling clock: rising edges at 5, 15, 25, ... ns
  logic clk_b = 0;                      // the second clock: rising edges at 2.6, 29.6, ... ns
  initial begin
    #2.6;
    forever begin clk_b = 1; #13.5; clk_b = 0; #13.5; end
  end
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so asynchronous resets act before any clock
  int edge_n = -1;                        // the number of the last rising edge of clk
  always @(posedge clk) edge_n = edge_n + 1;
  logic send_a = 0, ready_a, event_b;
  int sent = 0, got = 0, shown = 0;
  always @(posedge clk_b) if (event_b) got++;    // B counts the events it receives
  task automatic report();
    if (send_a) $display("e%0d A sends event %0d", edge_n, sent + 1);
    if (got != shown) begin shown = got; $display("e%0d B has received %0d", edge_n, got); end
  endtask
  event_link dut (.clk_a(clk), .clk_b(clk_b), .rst_n(rst_n), .send_a(send_a), .ready_a(ready_a), .event_b(event_b));
  // Advance to the next rising edge of clk, wait for the design to settle, then print.
  task automatic tick();
    @(posedge clk); #1;
    
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, clk edges 0 and 1 in reset, released 1 ns after edge 1
    repeat (3) begin
      while (!ready_a) tick();                 // wait until A may send
      send_a = 1; tick(); send_a = 0; sent++;  // one event, taken at this edge
      repeat (7) tick();
    end
    repeat (20) tick();
    $display("%0d sent, %0d received", sent, got);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule
// event_link: carries events from domain A (clk_a) to domain B (clk_b) with a toggle
// synchronizer. One reset pin feeds both domains; each releases it through its own reset
// synchronizer.
module event_link (
  input  logic clk_a,          // domain A: the sender
  input  logic clk_b,          // domain B: the receiver
  input  logic rst_n,          // the reset pin, shared by both domains
  input  logic send_a,         // domain A: 1 for one cycle per event to send
  output logic ready_a,        // domain A: 1 when an event may be sent
  output logic event_b         // domain B: 1 for one cycle per event received
);
  // Reset synchronizers: assert at once, release two edges of the domain's own clock later.
  logic ra_q1, rst_a_n, rb_q1, rst_b_n;
  always_ff @(posedge clk_a or negedge rst_n)
    if (!rst_n) begin ra_q1 <= 1'b0; rst_a_n <= 1'b0; end
    else        begin ra_q1 <= 1'b1; rst_a_n <= ra_q1; end
  always_ff @(posedge clk_b or negedge rst_n)
    if (!rst_n) begin rb_q1 <= 1'b0; rst_b_n <= 1'b0; end
    else        begin rb_q1 <= 1'b1; rst_b_n <= rb_q1; end

  // A: flip the toggle once per event.
  logic tog_a;
  always_ff @(posedge clk_a or negedge rst_a_n)
    if (!rst_a_n)    tog_a <= 1'b0;
    else if (send_a) tog_a <= ~tog_a;

  // A may send once its own reset is released.
  assign ready_a = rst_a_n;

  // B: two flops, then an edge detector on the synchronized toggle.
  logic t1, t2, t3;
  always_ff @(posedge clk_b or negedge rst_b_n)
    if (!rst_b_n) begin t1 <= 1'b0; t2 <= 1'b0; t3 <= 1'b0; end
    else          begin t1 <= tog_a; t2 <= t1; t3 <= t2; end
  assign event_b = t2 ^ t3;
endmodule