ASIC Point

Silicon Lab

Design Verification Problems

Build a design, hunt its bugs, or repair what fails. Every answer runs on a real simulator.

Build starts from a specification: make it work, then make it small or fast. Bug Hunt asks for the checker or the test that catches broken designs. Repair hands you a failure: find the cause, then fix the design.

Module 1 · Storing Data

  1. 1.1.1 Unknown-bit counter 675 Implement Easy Browser
  2. 1.1.4 Partial-knowledge scoreboard 1350 Implement Hard Browser
  3. 1.2.1 Byte-lane extraction 750 Implement Easy Browser
  4. 1.3.1 Header field decoder 750 Implement Easy Browser
  5. 1.4.1 Safe opcode decoder 825 Implement Easy Browser
  6. 1.4.2 State-transition validator 1200 Implement Medium Browser
  7. 1.6.1 Register index 750 Implement Easy Browser
  8. 1.7.7 Header monitor 1425 Implement Hard Browser

Module 2 · Collections

  1. 2.1.1 Resize and preserve 750 Implement Easy Verilator
  2. 2.2.1 First FIFO mismatch 825 Implement Easy Verilator
  3. 2.2.2 Bounded queue operations 1050 Implement Medium Verilator
  4. 2.3.1 Outstanding request lookup 750 Implement Easy Verilator
  5. 2.3.2 Duplicate-ID protection 975 Implement Medium Verilator
  6. 2.3.3 Out-of-order response matcher 1350 Implement Hard Verilator
  7. 2.4.2 Wide population reduction 825 Implement Easy Verilator
  8. 2.5.1 Missing beat indices 825 Implement Easy Verilator
  9. 2.6.1 Value snapshot 750 Implement Easy Verilator
  10. 2.7.1 Flush pending requests 750 Implement Easy Verilator

Module 3 · Routines and Processes

  1. 3.1.1 Popcount function 600 Implement Easy Verilator
  2. 3.3.1 Wait for two workers 750 Implement Easy Verilator
  3. 3.4.1 Persistent initialization flag 825 Implement Easy Verilator
  4. 3.5.1 Exact-count consumer 825 Implement Easy Verilator
  5. 3.7.1 Single-response deadline 900 Implement Easy Verilator
  6. 3.7.2 Inclusive boundary checker 1050 Implement Medium Verilator

Module 4 · Classes

  1. 4.1.1 Construct a valid packet 750 Implement Easy Verilator
  2. 4.3.1 Derived read transaction 825 Implement Easy Verilator
  3. 4.4.1 Virtual response length 750 Implement Easy Verilator
  4. 4.5.1 Safe downcast 825 Implement Easy Verilator
  5. 4.6.1 Typed value box 825 Implement Easy Verilator
  6. 4.7.1 Factory by opcode 825 Implement Easy Verilator
  7. 4.7.2 Validated factory arguments 1425 Implement Hard Verilator

Module 5 · Randomization

  1. 5.1.1 Legal packet length 825 Implement Easy Verilator
  2. 5.2.1 Legal value sets 825 Implement Easy Verilator
  3. 5.3.2 Balance mode frequency 825 Implement Easy Verilator
  4. 5.4.1 Override a soft default 825 Implement Easy Verilator
  5. 5.6.1 Replay one object stream 825 Implement Easy Verilator
  6. 5.7.1 Aligned burst request 825 Implement Easy Verilator

Module 6 · Connecting to the DUT

  1. 6.1.1 Typed bus connection 825 Implement Easy Verilator
  2. 6.4.1 Configure one driver 900 Implement Easy Verilator
  3. 6.5.2 Hold-until-accepted driver 1425 Implement Hard Verilator

Module 7 · FIFO Verification

  1. 7.1.1 Acceptance truth table 750 Implement Easy Verilator
  2. 7.2.2 Arbitrary-depth FIFO 1125 Implement Medium Verilator
  3. 7.3.1 Directed fill and drain 750 Implement Easy Verilator
  4. 7.4.1 FIFO expected queue 900 Implement Easy Verilator
  5. 7.5.8 Two coverpoints for the FIFO 825 Implement Easy Verilator

Protocols · P1 Protocol Fundamentals

  1. P1.3.1 Implement a sink 1125 Implement Medium Browser
  2. P1.4.1 Beats into transactions 750 Implement Easy Browser
  3. P1.6.2 A credit counter 975 Implement Medium Browser
  4. P1.7.1 A scoreboard keyed by tag 1200 Implement Medium Browser
  5. P1.9.1 A round-robin arbiter model 975 Implement Medium Browser
  6. P1.11.5 A monitor for the link 975 Implement Medium Browser

Protocols · P2 AXI

  1. P2.5.1 An issuer with N outstanding 1125 Implement Medium Browser
  2. P2.6.1 The address of every beat 1200 Implement Medium Browser
  3. P2.7.1 The lane mapper 1050 Implement Medium Browser
  4. P2.8.1 A byte-accurate write memory 1425 Implement Hard Browser
  5. P2.11.1 An ID-keyed scoreboard 1200 Implement Medium Browser
  6. P2.13.1 An exclusive monitor 1200 Implement Medium Browser
  7. P2.17.1 The AXI monitor 1350 Implement Hard UVM
  8. P2.18.6 A beat-to-transaction monitor 1425 Implement Hard Browser

UVM Practice

  1. U2.4.1 Pack a frame whose payload has its own length 1125 Implement Medium UVM
  2. U3.4.1 The trace window that never drops quietly 1050 Implement Medium UVM
  3. U5.3.1 A background sequence that leaves cleanly when killed 825 Implement Easy UVM
  4. U6.1.1 Keep a two-clock memory busy 1350 Implement Hard UVM
  5. U6.2.1 Play the memory, including its protected page 1125 Implement Medium UVM
  6. U6.3.1 Pack bytes into words, and flush the odd one 1350 Implement Hard UVM
  7. U8.2.1 Interleaved read bursts 1350 Implement Hard UVM
  8. U8.4.1 A latency meter with two bounds 1050 Implement Medium UVM
  9. U12.1.1 Inject a bad check on one lane, on chosen beats 1050 Implement Medium UVM