Subthreshold and leakage

A straight line on a log axis

Read the 27 °C curve of the hook from the left. It passes 1 nA at V_GS = 0.280 V and 10 nA at 0.374 V. Every further decade below the bend costs about the same gate voltage, so on a log axis the curve is a straight line.

Below the threshold the channel is only weakly inverted: too few electrons to carry current by drift. They cross from source to drain by diffusion, climbing an energy barrier that the gate lowers. The number that make it grows exponentially as the barrier falls, so I_D ∝ exp(V_GS/(n·U_T)). Here U_T = kT/q is the thermal voltage, 25.9 mV at 27 °C, and n is the slope factor: only 1/n of a gate change reaches the channel, so n is 1 at best.

The gate voltage for one decade of current is the subthreshold swing S = n·U_T·ln 10, in mV per decade. With n = 1 it is 59.6 mV/dec at 27 °C, and no MOSFET does better at room temperature. The lab measures s_27 = 94.0 mV/dec, so this device has n = 94.0/59.6 = 1.58, close to the 1.54 that E2.5's g_m/I_D limit gives for the same length at V_DS = 0.9 V.

The swing also predicts the off current. Start from 1 nA at 0.280 V and walk down 0.280/0.0940 = 2.98 decades to V_GS = 0: that gives 1.05 pA. The lab measures 1.02 pA. A threshold near 0.6 V and a swing near 94 mV/dec put the off current about six decades below the current at threshold.

Why heat raises the leakage

Two things move when the chip warms. The swing grows with temperature, because U_T = kT/q does. The threshold falls (E2.7 measures it), which slides the whole line to the left. Both raise the current at V_GS = 0.

The swing tracks absolute temperature within 0.3 %. So n hardly changes; the physics is U_T. The off current rises 79 times from −40 °C to 27 °C and 150 times more by 125 °C: over four decades across the range a product must work in.

The drain matters too. At V_DS = 0.1 V the lab measures ioff_vds01 = 1.034624e-13, ten times less than at 1.8 V. A high drain voltage lowers the source barrier (drain-induced barrier lowering, E2.2), and in subthreshold every millivolt of barrier is exponential.

Weak inversion is not only a nuisance. The same exponential gives the highest g_m/I_D a transistor can have (E2.5), and low-power analog circuits bias there on purpose.

The simulator's own leak

SPICE adds a tiny conductance called gmin across the device junctions, 10⁻¹² S unless you change it, to help the solver converge. It is invisible in most circuits. At 1.8 V it carries 1.8 pA, and that is more than this transistor's own off current.

.lib sky130 tt
.options temp=-40
XM1 d g 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15
VDS d 0 1.8
VGS g 0 0
.control
dc VGS 0 0.6 0.002
let id = -i(VDS)
meas dc ioff FIND id AT=0
.endc

.lib sky130 tt
.options temp=-40 gmin=1e-18
XM1 d g 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15
VDS d 0 1.8
VGS g 0 0
.control
dc VGS 0 0.6 0.002
let id = -i(VDS)
meas dc ioff FIND id AT=0
.endc

Try it

Run the netlist. Each dc sweep is followed by two meas lines: the current at V_GS = 0, and TRIG ... TARG, which returns the V_GS step between the 1 nA and 10 nA crossings. That step is the swing in volts per decade. option temp=125 sets the temperature for the next analysis.

Now delete the .options gmin=1e-18 line and run again. Predict which readings move: the three off currents should each grow by about 1.8 pA, which only matters where the device leaks less than that. Then open Plots and compare the slopes of the three temperatures.

Check yourself

* an ideal subthreshold device: S = 100 mV/dec, 1 uA at VGS = 0.5 V
VDS d 0 1.8
VGS g 0 0.5
B1 d 0 I = 1e-6*exp((v(g)-0.5)*2.302585093/0.1)
.control
dc VGS 0 0.6 0.01
let id = -i(VDS)
meas dc id_low FIND id AT=0.3
.endc
.end