Corners and temperature

Five corners of one process

No two wafers come out of a factory alike. The gate oxide is a little thicker or thinner, the implants a little heavier or lighter, so thresholds and mobilities shift. A process corner is a set of model parameters for a wafer at the edge of that spread. In a fast corner a device carries more current at the same bias; in a slow one, less.

SKY130 ships five FET corners, chosen with .lib sky130 tt|ff|ss|sf|fs: typical (tt), both fast (ff), both slow (ss) and two skewed corners in which one kind is fast and the other slow. A corner moves every device on the die together. Two neighbouring devices that differ from each other show mismatch, a separate effect (E7).

Short devices swing much more than long ones, and the PMOS more than the NMOS. Now read the skewed rows. In the corner named sf the NMOS is fast at both sizes, as fast as ff at L = 0.15 µm and faster than ff at L = 1 µm. Its PMOS is slow, and at L = 1 µm slower than in ss. The corner named fs is the mirror image.

The comment at the top of the PDK's sky130.lib.spice describes sf as slow N, fast P. The parameters in parameters_fet_sf.spice do the opposite, at both sizes we measured. So read a corner name as a label, and learn what each corner does from your own devices. In this track sf means fast NMOS, slow PMOS, because that is what it simulates.

Temperature pulls two ways

Heat changes the same device in two opposite ways. The threshold falls: the lab extracts 0.726 V at −40 °C, 0.676 V at 27 °C and 0.612 V at 125 °C, about −0.69 mV per kelvin. Lower threshold, more current. Mobility also falls, because a hotter lattice scatters the carriers more often. Lower mobility, less current.

So "hot is slow" holds only with plenty of gate drive. A gate driven from the full 1.8 V supply is slowest at 125 °C. A circuit whose devices see less than about 1 V of drive is slowest when cold. That reversal is called temperature inversion, and it is why timing sign-off checks both ends of the temperature range.

Corners and temperature combine. A design is checked at process, voltage and temperature together (PVT): for example ss at 125 °C for a fully driven gate, and ss at −40 °C for a weakly driven one. E7 builds that sign-off table for an amplifier.

Try it

Run the netlist: the first sweep moves every gate together, and meas reads the four currents of the table's tt row. The second part extracts the threshold at three temperatures with the constant-current method of E2.2.

Now change the first line after the title to .lib sky130 sf and run again; then try fs. Before each run, predict the sign of every change against tt. One run loads one corner: the library is read when the netlist loads, so five corners take five runs.

Check yourself

* does the current at VGS = 0.9 V rise or fall from 27 C to 125 C?
.lib sky130 tt
XM1 d g 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15
VDS d 0 1.8
VGS g 0 0
.control
dc VGS 0 1.8 0.01
option temp=125
dc VGS 0 1.8 0.01
let id_27 = -dc1.vds#branch
let id_125 = -i(VDS)
* rises is 1 where the hot current is larger, 0 where it is smaller
let rises = id_125 gt id_27
meas dc rises_at_09 FIND rises AT=0.9
.endc
.end