Channel-length modulation and output resistance

Why the saturated current keeps rising

In saturation the channel pinches off near the drain. Raise V_DS and the pinch-off point moves toward the source, so the channel that carries the current gets shorter. A shorter channel passes more current: channel-length modulation. In short devices the drain also lowers the source barrier (DIBL, E2.2), which adds to the rise.

The slope of the saturated curve is the output conductance g_ds = ∂I_D/∂V_DS. Its inverse, r_o = 1/g_ds, is the output resistance. Seen from the drain, a transistor in saturation is a current source in parallel with r_o.

Extend the tangent of the saturated curve backward to zero current. It crosses the voltage axis at −V_A; V_A is the Early voltage. From the tangent, V_A = I_D/g_ds − V_DS. When V_A is much larger than V_DS, r_o ≈ V_A/I_D, and the textbook λ is about 1/V_A.

To measure g_ds in SPICE, hold the gate and sweep the drain, then differentiate the current with let gds=deriv(id). meas ... FIND gds AT=0.9 reads it at the operating point. One op would give a single number; the sweep also shows how that number changes as V_DS moves, which matters below.

Output resistance against length

The lab sizes four NMOS devices for about 20 µA at V_GS = V_DS = 0.9 V, at L = 0.15, 0.5, 1 and 2 µm. It measures g_ds from a drain sweep and g_m = ∂I_D/∂V_GS from a gate sweep. The figure shows the shortest and the longest.

Read r_o where the circuit sits. Just above V_Dsat the curve is still bending and r_o is small; deeper in saturation it settles. A stage biased near the edge of saturation therefore has less gain than the table promises, a trap that returns whenever output swing pushes V_DS down.

V_A grows with length, but not in proportion: 7.8 V per µm of L at 0.15 µm, 20.5 at 0.5 µm, then 13.0 and 11.4. The short device loses most to DIBL, which a longer channel quickly removes.

Intrinsic gain, the first design trade

The intrinsic gain g_mr_o = g_m/g_ds is the highest voltage gain one transistor can give: its own current source driving its own r_o. Written as (g_m/I_D)·(V_A + V_DS), it shows the two levers: how much g_m each microamp buys, and how large V_A is.

From 0.15 to 2 µm the lab's intrinsic gain rises from 16.7 to 131, nearly eight times. That is the first design trade of the track. Long channels give gain and, later, better matching. Short channels give speed and small area. Analog designers rarely use minimum length where gain matters.

XN1 d1 g 0 0 sky130_fd_pr__nfet_01v8 W=0.6 L=0.15

XN4 d4 g 0 0 sky130_fd_pr__nfet_01v8 W=3.2 L=2

E3 uses this number at once. A common-source amplifier whose load is an ideal current source has a gain of −g_mr_o, the intrinsic gain itself. Any real load only lowers it, so g_m/g_ds is the ceiling for every single-transistor stage built on that device.

The hook's λ = 0.1 V⁻¹ sits between these devices and matches none of them at this bias. To use λ at all, fit it to the device you will use: λ ≈ 1/V_A from the table, at the V_DS where the circuit sits.

Try it

The first sweep moves the gate around 0.9 V and keeps g_m for each device. The second sweeps the drain; dc1.gm1[100] reads point 100 of the first sweep, V_GS = 0.9 V, so gain1 is g_m/g_ds along the drain sweep. Open Plots and look at ro_short and ro_long.

Change VGS to 1.2 V (and the first sweep to 1.1 1.3 0.001) and rerun. Predict first: the current rises, so r_o should fall. Does g_m/g_ds rise or fall?

Check yourself

* the g_ds bench with an ideal 20 uA current source in place of the transistor
VDS d 0 0.9
VA d d1 0
I1 d1 0 20u
.control
dc VDS 0 1.8 0.005
let gds=deriv(i(VA))
meas dc gds FIND gds AT=0.9
.endc
.end