Enables and gated clocks

An enable belongs on the data path

A register that must hold its value in some cycles needs an enable: a condition inside the clocked block, if (en) q <= d;. The clock reaches the flop on every edge. At each edge the flop takes either the new value or its own old one, decided by en.

assign gclk = clk & en;
always_ff @(posedge gclk or negedge rst_n)
  if (!rst_n) wptr <= 3'd0;
  else        wptr <= wptr + 3'd1;

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n)  wptr <= 3'd0;
  else if (en) wptr <= wptr + 3'd1;

Synthesis builds the enable as a flop with an enable pin, or as a flop with a multiplexer that feeds the old value back. Either way the decision sits on the data path, where the flop's setup time protects it. The cell names in the Gates tab say which kind of flop you got.

Why the AND gate adds edges

An enable made by a flop changes a moment after the rising edge, while the clock is still high. That is the worst moment for an AND gate. A rising en raises gclk at once, and a falling en cuts the clock pulse short.

Two more rules follow. A clock is never made by logic inside the design: a divider is a counter that produces an enable, and the block stays on one clock. A clock is never used as data either.

Clock gating done right: the ICG cell

Stopping the clock does save power, and chips do it everywhere. They use an integrated clock-gating cell (ICG), a library cell with a latch in front of the AND gate. The latch is open while clk is low and closed while it is high, so the enable cannot change during a high phase.

A real flow inserts ICGs from enables you wrote, or you instantiate the library's cell by name. Yosys has a clockgate command for this, but it needs a cell library. This site's flow maps to built-in gates, which include no ICG, so here clock gating stays a description.

// A model of a clock-gating cell, for reading. In a chip this is one
// library cell, inserted by the flow or instantiated; never hand-written.
logic en_l;
always_latch if (!clk) en_l = en;   // open while clk is low, closed while it is high
assign gclk = clk & en_l;

The lab ships the AND-gated version. Run it and read the doubled entries in the log line. Then move the enable into the two blocks and run again.

Try it

Four values were written and the log holds six: 11 and 44 twice. Each time en rose while clk was high, gclk had an extra edge. Synthesize: 174 cells and 67 flops, every one clocked by the AND output.

Delete gclk and its assign, clock both blocks with clk, and add the enable: else if (en) wptr <= wptr + 3'd1; and if (en) mem[wptr] <= din;. Run again: the pointer ends at 4 and the log reads 11 22 33 44 xx xx xx xx. Synthesize: 176 cells, 67 flops, all on clk; the pointer flops are now $_DFFE_PN0P_.

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic       rst_n = 1;
  logic       en = 0;
  logic [7:0] din = 0;
  logic [2:0] raddr = 0;
  logic [7:0] rdata;
  logbuf dut (.clk(clk), .rst_n(rst_n), .en(en), .din(din), .raddr(raddr), .rdata(rdata));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    $display("e%0d en=%b din=%h wptr=%0d", edge_n, en, din, dut.wptr);
  endtask
  initial begin
    #1 rst_n = 0;                           // reset asserted before edge 0
    tick(); tick(); rst_n = 1;              // released 1 ns after edge 1
    tick();                                 // e2: idle
    // From here en and din change 1 ns after an edge, while clk is still high,
    // the way the output of a flop clocked by clk would.
    din = 8'h11; en = 1; tick();            // e3: three writes, one per edge ...
    din = 8'h22;         tick();            // e4
    din = 8'h33;         tick();            // e5
    en = 0;              tick();            // e6: ... then nothing to write
                         tick();            // e7
    din = 8'h44; en = 1; tick();            // e8: one more write
    en = 0;              tick();            // e9
    $write("log:");                         // read the log back, entry 0 first
    for (int i = 0; i < 8; i++) begin
      raddr = i; #1 $write(" %h", rdata);
    end
    $display("");
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

Check yourself

module tb;
  logic clk = 0, rst_n = 0, en = 0;
  logic [7:0] d = 0, q;
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n)  q <= 8'd0;
    else if (en) q <= d;
  task automatic step(); #5 clk = 1; #5 clk = 0; endtask
  initial begin
    step();                       // one edge in reset: q = 0
    rst_n = 1;
    en = 1; d = 8'd7; step();
    d = 8'd9;         step();
    en = 0; d = 8'd4; step();
    d = 8'd5;         step();
    $display("q=%0d", q);
    $finish(0);
  end
endmodule

logic gclk;
assign gclk = clk & en;
always_ff @(posedge gclk or negedge rst_n)
  if (!rst_n) q <= 4'd0;
  else        q <= q + 4'd1;

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n)  q <= 4'd0;
  else if (en) q <= q + 4'd1;

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) q <= 4'd0;
  else        q <= en ? q + 4'd1 : q;

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) q <= 4'd0;
  else        q <= q + {3'd0, en};