always_ff, old state and next state

Old state and next state in one edge

A clocked block runs once per rising edge. At that moment every register has an old state, the value it held before the edge, and the block computes each register's next state from the old states. A blocking assignment (=) breaks that picture: the variable changes at once, and the next statement in the block reads the changed value. A nonblocking assignment (<=) reads every right-hand side first and updates every variable afterwards, in the same time step, so each statement sees old state only.

always_ff @(posedge clk)
begin
  s1 = d;
  q  = s1;   // reads the new s1
end

always_ff @(posedge clk)
begin
  s1 <= d;
  q  <= s1;  // reads the old s1
end

Note what did not happen: simulation and synthesis did not disagree. Both follow the language, which says a blocking assignment completes before the next statement. The failure is that the code did not say what the designer meant. Verilator says so at lint time: %Warning-BLKSEQ: Blocking assignment '=' in sequential logic process, once per =.

The race between two blocks

The second failure is older and nastier. Put the two stages in two clocked blocks, both with blocking assignments. At one edge both blocks are ready to run, and the language lets the simulator run them in either order. Run q = s1 first and q gets the old s1: two stages. Run s1 = d first and q gets the new s1: one stage. The same source can behave either way in two simulators, or in one simulator after an unrelated edit, and a netlist always has two registers. This is the simulation-against-synthesis mismatch blocking assignments are famous for, and it needs two blocks, not one.

Measured on Icarus 12 with this lesson's bench and d stepping 1 to 5: with the s1 block written first, q read 1, 1, 3, 3, 5 at edges 2 to 6; with the q block written first, 0, 2, 2, 4, 4. Neither is a pipeline. Yosys 0.70 builds 16 flops from either file.

always_ff @(posedge clk) s1 = d;    // which runs first?
always_ff @(posedge clk) q  = s1;   // old s1 or new s1: the simulator decides

Nonblocking assignments end the question. A simulator splits each time step into regions. In the active region every ready block runs its statements and reads the old state. Nonblocking updates wait for the nonblocking-assignment region, after the active statements, so every register updates afterwards, whatever the order the blocks ran in. That is the whole reason for the rule: registers are written with <=, always, and a clocked block never reads a value another clocked block wrote in the same edge.

Reading a clocked block

1. Find the registers

   Every variable assigned in an always_ff block is a register, one flop per bit. Count them; the netlist will agree.

2. Read right-hand sides as old state

   With <=, every right-hand side in the block is the value before the edge. The order of the statements does not matter for the result.

3. Treat a repeated target as the last word

   Two nonblocking assignments to the same variable in one block: the last one wins. That is how a reset or a clear takes priority (R2.6).

4. Treat a blocking assignment as a flag

   An = in a clocked block is either a temporary (a named wire the block uses on the same edge) or a bug. Verilator warns on every one; make the temporary an always_comb variable instead.

The lab ships the pipeline with =. Run it: q equals d at every edge, and the Gates tab shows eight flops. Change the two assignments to <=, run again, and q trails d by two edges, with sixteen flops. The reset assignments may stay blocking or become nonblocking; the netlist is the same either way, and nonblocking everywhere is the house style.

Try it

Edges 0 and 1 are in reset. From edge 2 the input counts up, and at every edge q already equals d: the second statement read the s1 the first statement had just written. One stage.

Change s1 = d; q = s1; to s1 <= d; q <= s1; and run again. Now s1 takes d at each edge and q takes it one edge later: at edge 4 the line reads d=3 s1=3 q=2. Synthesize both versions and compare the flop counts: 8 and 16.

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic [7:0] d = 0;
  logic [7:0] q;
  pipe2 dut (.clk(clk), .rst_n(rst_n), .d(d), .q(q));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    $display("e%0d d=%0d s1=%0d q=%0d", edge_n, d, dut.s1, q);
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    for (int i = 1; i <= 6; i++) begin
      d = i; tick();
    end
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

Check yourself

module tb;
  logic clk = 0, rst_n = 1;
  logic [3:0] a, b;
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin a <= 4'd1; b <= 4'd0; end
    else begin
      b <= a;        // nonblocking: both right-hand sides are read first ...
      a <= b;        // ... then both variables change together
    end
  initial begin
    #1 rst_n = 0;                 // reset pulse: a = 1, b = 0
    #1 rst_n = 1;
    #1 clk = 1; #1 clk = 0;
    #1 clk = 1; #1 clk = 0;
    #1 clk = 1; #1 clk = 0;
    $display("a=%0d b=%0d", a, b);
    $finish(0);
  end
endmodule

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) begin s1 = 0; q = 0; end
  else begin s1 = d; q = s1; end

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) begin s1 <= 0; q <= 0; end
  else begin s1 <= d; q <= s1; end

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) s1 <= 0; else s1 <= d;
always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) q <= 0; else q <= s1;

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) begin s1 <= 0; q <= 0; end
  else begin q <= s1; s1 <= d; end