Reset: assert, release, and what RTL cannot show

Assertion: at once or at the next edge

A reset has two moments. Assertion puts every register into its reset state. Release (also called removal) lets the registers follow their inputs again. The two reset styles differ in when assertion acts.

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) a_q <= 4'd0;
  else        a_q <= a_q + 4'd1;

always_ff @(posedge clk)
  if (!rst_n) s_q <= 4'd0;
  else        s_q <= s_q + 4'd1;

An asynchronous reset works before the clock runs, which is what a chip needs at power-up. A synchronous reset needs edges, and it needs reset to be low at one of them. The lab bench shows what happens when it is not.

Release: the moment simulation cannot show

Assertion is safe in both styles. Release is where an asynchronous reset gets dangerous. A flop with an asynchronous reset has a recovery time: the release must arrive at least that long before the next rising edge. It also has a removal time: the release must not come sooner than that after the edge. These are the reset-side names for setup and hold.

Release inside that window and the flop may leave reset a cycle early or late, or go metastable: its output hovers between 0 and 1 for a while before settling. Two flops of one block can land on different sides of the window, as in the hook.

The cure is the reset synchronizer. The pin still asserts the domain's reset at once. Its release goes through two flops clocked by the domain's clock, so it reaches every register just after an edge, a whole period before the next one.

Three rules for reset code

1. Reset first, alone

   The reset test is the first if of the block, and everything else sits in its else.

2. Reset every register of the block

   A register left out of the reset branch is unknown until something loads it. Leave one out only when the brief says so, and give it its own block.

3. Never treat the reset as data

   Do not read rst_n in the non-reset branch, and do not gate or derive it with logic inside the domain.

The lab ships without the synchronizer, and reset_sync.sv sits beside it, read-only. Run it and find the pulse that cleared one counter only. Then put the synchronizer in and run again.

Try it

Without a synchronizer, both counters count from edge 2. The pulse after edge 5 clears a_q at once and misses s_q, so from edge 6 the counters disagree. Synthesize: 20 cells, four $_DFF_PN0_ flops for a_q and four $_SDFF_PN0_ for s_q.

Replace the assign line with reset_sync u_rs (.clk(clk), .rst_n_in(rst_n), .rst_n_out(rst_n_sync)); and run again. Both counters now count from edge 4. The pulse still clears a_q at once, sync stays low through edge 6, and both counters count together from edge 8. Synthesis grows to 22 cells and 10 flops.

Then delete the reset from the s_q block, leaving s_q <= s_q + 4'd1;. Every line prints s_q=x: an unknown value plus one is still unknown.

// reset_sync.sv: asynchronous assertion, synchronous release (read-only).
// rst_n_in may fall at any time and the output falls with it; when rst_n_in rises, the output rises
// two rising edges later, so every flop in the domain leaves reset in the same cycle.
module reset_sync (input logic clk, input logic rst_n_in, output logic rst_n_out);
  logic q1;
  always_ff @(posedge clk or negedge rst_n_in)
    if (!rst_n_in) begin q1 <= 1'b0; rst_n_out <= 1'b0; end
    else begin q1 <= 1'b1; rst_n_out <= q1; end
endmodule

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic       rst_n = 1;
  logic [3:0] a_q, s_q;
  rst_demo dut (.clk(clk), .rst_n(rst_n), .a_q(a_q), .s_q(s_q));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    $display("e%0d rst_n=%b sync=%b a_q=%0d s_q=%0d", edge_n, rst_n, dut.rst_n_sync, a_q, s_q);
  endtask
  initial begin
    #1 rst_n = 0;                           // power-on reset, asserted before edge 0
    tick(); tick(); rst_n = 1;              // released 1 ns after edge 1
    repeat (4) tick();                      // e2 .. e5
    #3 rst_n = 0;                           // a 5 ns reset pulse: falls 4 ns after edge 5 ...
    #1 $display("e5+5ns rst_n=%b sync=%b a_q=%0d s_q=%0d", rst_n, dut.rst_n_sync, a_q, s_q);
    #4 rst_n = 1;                           // ... and rises 1 ns before edge 6
    repeat (5) tick();                      // e6 .. e10
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

Check yourself

module tb;
  logic clk = 0, rst_n = 0;
  logic [3:0] a, s;
  always_ff @(posedge clk or negedge rst_n)     // asynchronous reset
    if (!rst_n) a <= 4'd0; else a <= a + 4'd1;
  always_ff @(posedge clk)                      // synchronous reset
    if (!rst_n) s <= 4'd0; else s <= s + 4'd1;
  initial begin
    #5 clk = 1; #5 clk = 0;                     // one edge in reset: a = 0, s = 0
    rst_n = 1;
    repeat (3) begin #5 clk = 1; #5 clk = 0; end
    #2 rst_n = 0;                               // reset falls between edges
    #1 $display("a=%0d s=%0d", a, s);
    $finish(0);
  end
endmodule

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) c <= '0;
  else begin
    if (en) c <= c + 4'd1;
    hit <= hit | (c == 4'd15);
  end

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) c <= '0;
  else if (en) c <= c + 4'd1;
always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) hit <= 1'b0;
  else hit <= hit | (c == 4'd15);

always_ff @(posedge clk)
  if (!rst_n) begin c <= '0; hit <= 1'b0; end
  else begin
    if (en) c <= c + 4'd1;
    hit <= hit | (c == 4'd15);
  end

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) begin c <= '0; hit <= 1'b0; end
  else begin
    if (en) c <= c + 4'd1;
    hit <= hit | (c == 4'd15);
  end