Counters and the wrap

Three decisions in every counter

A counter is a register, an adder and a decision about the next value. Three things must be written down before the RTL. The width: a W-bit register holds 0 to 2^W - 1 and wraps to 0 on its own. The terminal count: the value after which the counter returns to 0, when the range is not a power of two. And which value is the last one held.

The terminal count is the last value held

Read the hook trace again. The compare uses 10, the first value outside the range. So the counter must first reach 10 before the compare can see it, and 10 is held for a cycle. Compare with N - 1, the last value inside the range, and the register goes from 9 straight to 0.

localparam logic [W-1:0] LAST = W'(N);
assign tc = (count == LAST);

localparam logic [W-1:0] LAST = W'(N - 1);
assign tc = (count == LAST);

tc marks the cycle that holds the last value. A next stage, such as the tens digit of a clock, adds one when tc is 1. It acts on the same edge that wraps this counter, so both change together.

Never assume the period: count it. The bench prints every edge across two wraps. Subtract the edge numbers of two tc pulses and you have the period.

When the compare can never be true

The 0-to-19 copy compared a 4-bit count with 5'd19. For ==, both operands are first widened to the larger width. So count gets a 0 on top, and its largest value is 15. The compare is false forever, and the counter wraps at 16 on its own.

The synthesizer sees the same thing. A compare that is always false is a constant 0, so it removes the compare and the mux. Measured on this flow, that design is 10 cells and 3 levels of logic, the same as a plain 4-bit counter. Lint is more helpful: Verilator says %Warning-WIDTHEXPAND: Operator EQ expects 5 bits on the LHS, but LHS's VARREF 'count' generates 4 bits.

The lab ships the counter that compares with N. Run it and find tc at edges 11 and 22. Change W'(N) to W'(N - 1) and run again: tc at edges 10 and 20. Then set the parameter to 12 and count the period again. Synthesize each: 16 cells for N = 10, 14 cells for N = 12, 4 flops in both.

Try it

Edges 0 and 1 are in reset. From edge 2 the counter climbs, reaches 10 at edge 11 with tc = 1, and loads 0 at edge 12. The next tc is at edge 22: eleven edges per turn.

Fix the terminal count to W'(N - 1) and the lines read 9 with tc = 1 at edges 10 and 20, then 0. Set N = 12 and tc comes at edges 12 and 24.

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic [3:0] count;                      // wide enough for N up to 16
  logic       tc;
  modn dut (.clk(clk), .rst_n(rst_n), .count(count), .tc(tc));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    $display("e%0d count=%0d tc=%0b", edge_n, count, tc);
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    repeat (24) tick();
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

Check yourself

module tb;
  logic clk = 0, rst_n = 1;
  logic [2:0] count;                 // 3 bits: 0 .. 7, then wraps
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) count <= '0;
    else        count <= count + 1'b1;
  initial begin
    #1 rst_n = 0;                    // reset: count = 0
    #1 rst_n = 1;
    repeat (10) begin #1 clk = 1; #1 clk = 0; end
    $display("count=%0d", count);
    $finish(0);
  end
endmodule

logic tc;
assign tc = (count == 3'd5);
always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) count <= '0;
  else        count <= count + 1'b1;

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n)              count <= '0;
  else if (count == 3'd5)  count <= '0;
  else                     count <= count + 1'b1;

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n)              count <= '0;
  else if (count >= 3'd5)  count <= '0;
  else                     count <= count + 1'b1;

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) count <= '0;
  else        count <= (count == 3'd5) ? 3'd0 : count + 3'd1;