Capstone: a programmable timer

// timer: a programmable timer with a prescaler, periodic and one-shot modes.
// Registers, written through we/addr/wdata (one write per cycle):
//   addr 0 CTRL     bit 0 enable, bit 1 one-shot (0: periodic)
//   addr 1 PERIOD   1..255: pulse every PERIOD steps
//   addr 2 PRESCALE 1..15: one step every PRESCALE cycles (0 acts as 1)
// A write to CTRL or PERIOD restarts the count from PERIOD.
module timer (
  input  logic       clk,
  input  logic       rst_n,
  input  logic       we,
  input  logic [1:0] addr,
  input  logic [7:0] wdata,
  output logic [7:0] count,      // the main counter, counting down
  output logic       pulse,      // one cycle wide, every PERIOD steps
  output logic       running
);
  logic       oneshot_q;
  logic [7:0] period_q;
  logic [3:0] prescale_q, pre_q;

  wire wr_ctrl   = we && addr == 2'd0;
  wire wr_period = we && addr == 2'd1;
  wire wr_pre    = we && addr == 2'd2;

  // Register writes.
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin
      oneshot_q <= 1'b0; period_q <= 8'd1; prescale_q <= 4'd1;
    end else begin
      if (wr_ctrl)   oneshot_q  <= wdata[1];
      if (wr_period) period_q   <= wdata;
      if (wr_pre)    prescale_q <= wdata[3:0];
    end

  // The prescaler: step is 1 in one cycle out of PRESCALE while running.
  wire pre_tc = (pre_q + 4'd1 >= prescale_q);
  wire step   = running && pre_tc;
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n)                      pre_q <= '0;
    else if (wr_ctrl || wr_period)   pre_q <= '0;            // restart
    else if (running)                pre_q <= pre_tc ? 4'd0 : pre_q + 4'd1;

  // The main counter: loads PERIOD, counts down one per step, reloads at the terminal count.
  wire tc = step && (count == 8'd1);
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin
      count <= 8'd0; running <= 1'b0; pulse <= 1'b0;
    end else begin
      pulse <= tc;
      if (wr_ctrl || wr_period) begin                       // restart
        count   <= wr_period ? wdata : period_q;
        if (wr_ctrl) running <= wdata[0];
      end else if (tc) begin
        if (oneshot_q) begin count <= 8'd0; running <= 1'b0; end   // stop
        else           count <= period_q;                         // reload
      end else if (step)
        count <= count - 8'd1;
    end
endmodule

module tb;
  logic clk = 0, rst_n = 1, we = 0;
  logic [1:0] addr = 0;
  logic [7:0] wdata = 0, count;
  logic       pulse, running;
  int pulses = 0, n = 0, prev = -1, bad = 0;
  timer dut (.clk(clk), .rst_n(rst_n), .we(we), .addr(addr), .wdata(wdata),
             .count(count), .pulse(pulse), .running(running));
  task automatic edge1(); #1 clk = 1; #1 clk = 0; n++; endtask
  task automatic write(input logic [1:0] a, input logic [7:0] v);
    we = 1; addr = a; wdata = v; edge1(); we = 0;
  endtask
  initial begin
    #1 rst_n = 0;
    #1 rst_n = 1;
    write(2, 1);                         // PRESCALE 1
    write(1, 5);                 // PERIOD 5
    write(0, 8'b01);                     // CTRL: enable, periodic
    repeat (20) begin
      edge1();
      if (pulse) begin
        pulses++;
        if (prev >= 0 && n - prev != 5) bad++;
        prev = n;
      end
    end
    $display("pulses=%0d", pulses);
    $finish(0);
  end
endmodule