ASIC Point

Silicon Lab

Digital Design Problems

Build a design, hunt its bugs, or repair what fails. Every answer runs on a real simulator.

Build starts from a specification: make it work, then make it small or fast. Bug Hunt asks for the checker or the test that catches broken designs. Repair hands you a failure: find the cause, then fix the design.

RTL Design · R1 From Spec to Gates

  1. R1.1.1 A four-input mux 675 Implement Easy Simulation + synthesis
  2. R1.2.1 An occupancy counter from a brief 900 Implement Easy Simulation + synthesis
  3. R1.5.1 A priority encoder with a collision flag 975 Implement Medium Simulation + synthesis
  4. R1.7.1 The largest of N 1050 Implement Medium Simulation + synthesis

RTL Design · R2 Registers, Resets and Time

  1. R2.4.1 A digit counter with a carry 825 Implement Easy Simulation + synthesis
  2. R2.5.1 One press, one pulse 1200 Implement Medium Simulation + synthesis
  3. R2.7.1 A programmable timer 1500 Implement Hard Simulation + synthesis

RTL Design · R3 Finite State Machines

  1. R3.1.1 An acknowledge that waits for the edge 900 Implement Easy Simulation + synthesis
  2. R3.4.1 Frame marks that overlap 1200 Implement Medium Simulation + synthesis
  3. R3.5.1 An APB GPIO block 1425 Implement Hard Simulation + synthesis
  4. R3.6.1 A UART transmitter with no gaps 1575 Implement Hard Simulation + synthesis

RTL Design · R4 Timing and Pipelining

  1. R4.3.1 An adder tree with its valid pipe 900 Implement Easy Simulation + synthesis
  2. R4.4.1 A skid buffer 1125 Implement Medium Simulation + synthesis

RTL Design · R5 Memories, FIFOs and Arbiters

  1. R5.1.1 Two reads and a write 900 Implement Easy Simulation + synthesis
  2. R5.2.1 A FIFO of any depth 1275 Implement Medium Simulation + synthesis
  3. R5.4.1 A round robin for any N 1275 Implement Medium Simulation + synthesis
  4. R5.6.1 A merger that favours A two to one 1575 Implement Hard Simulation + synthesis

RTL Design · R6 Clock Domain Crossing

  1. R6.3.1 One event, one byte 1125 Implement Medium Simulation + synthesis
  2. R6.4.1 A Gray pointer 825 Implement Easy Simulation + synthesis
  3. R6.6.1 The asynchronous FIFO 1725 Implement Expert Simulation + synthesis

RTL Design · R7 RTL That Others Can Read and Verify

  1. R7.1.1 An interrupt block behind an interface 1275 Implement Medium Simulation + synthesis

RTL Design · R8 Capstones

  1. R8.1.1 A GPIO-and-timer peripheral 1650 Implement Hard Simulation + synthesis
  2. R8.2.1 A UART receiver on APB 1875 Implement Expert Simulation + synthesis
  3. R8.3.1 An AXI-Stream packet filter 1500 Implement Hard Simulation + synthesis