The simple mirror and its errors

Copying a current with two transistors

Push a reference current I_REF into a transistor whose gate is tied to its drain. This diode-connected transistor cannot leave saturation: its V_DS equals its V_GS, which is always more than V_GS − V_th. It settles at the one V_GS that carries I_REF.

Give a second transistor the same V_GS. In saturation its current depends mainly on V_GS, so it carries about the same current. That pair is a current mirror: M1 turns a current into a voltage, and M2 turns the voltage back into a current. Neither gate draws current, so one reference can feed many outputs.

The copy flows from whatever drives the output node. The reference only sets the gate voltage. Making M2 m units of M1 scales the copy by m: the lab's 2:1 output (m=2) carries 40.53 µA at 0.9 V, exactly twice the 1:1 copy of 20.27 µA.

The lab measures each output with a 0 V source between node o and the device. SPICE counts a source's current as positive when it flows into the + terminal. Current flows from o into each output device, so these ammeters read positive.

Where the copy is exact, and why it drifts

Step through the measured copy of the two extreme lengths. The upper panel is the current; the lower one is the output resistance r_out = 1/(∂I_out/∂V_out), on a log axis.

The copy is exact at one output voltage only: V_out = V_GS, where M2 sees exactly what M1 sees. Anywhere else M2's V_DS differs from M1's, and a saturated transistor's current still rises with V_DS. That rise is channel-length modulation, plus drain-induced barrier lowering (DIBL) in short devices, from the E2 lesson "Channel-length modulation and output resistance".

With the first-order model I_D ∝ (1 + λV_DS), the copy ratio is I_out/I_REF ≈ (1 + λV_DS2)/(1 + λV_DS1). Seen from the output, the mirror is a current source in parallel with M2's own r_o, so r_out = r_o2.

Check the model on the 8/1 mirror. Start at the exact point, 20 µA at 0.714 V, and climb with slope 1/r_out = 1/731 kΩ. At 0.9 V that predicts 20 + 0.186 V/731 kΩ = 20.26 µA; the run gives 20.27 µA. For 2/0.15 µm the same line predicts 21.83 µA from V_GS = 0.771 V and 70.7 kΩ; the run gives 21.83 µA.

Longer devices copy better, twice over. Their r_out is higher: ten times higher at 1 µm than at 0.15 µm. They also need less V_GS for the same W/L (0.771 V down to 0.687 V), which leaves more room below the output. Short devices need extra gate voltage because of velocity saturation (E2 lesson "The square law and where SKY130 departs from it"). SKY130's threshold is also highest at L = 0.15 µm ("Threshold and the regions").

The gain flattens out. From 1 to 2 µm, r_out moves only from 731 to 735 kΩ at this bias, while the gate area W·L grows from 8 to 32 µm². A bigger gate also adds capacitance, so the gate line settles more slowly. L = 1 µm is the usual choice in this module.

How low the output can go

Below some output voltage M2 moves toward triode and the copy falls away. This module defines the minimum output voltage once and uses it for every mirror: the output voltage at which the current is 1 % below its value at V_out = 0.9 V. The lab finds it with meas ... WHEN n_1=0.99, where n_1 is the current divided by its value at 0.9 V.

For the simple mirror the result is set by the slope as much as by the knee. The 8/1 copy falls 1 % at 0.757 V, but most of that drop is the steady slope of r_out, not M2 leaving saturation: at 0.2 V it still carries 18.64 µA. For 2/0.15 µm the slope alone loses 1 % within 15 mV, at 0.885 V.

The knee shows in the lower panel. The 8/1 device's r_out is 731 kΩ at 0.9 V, 295 kΩ at 0.3 V and 112 kΩ at 0.2 V. A real circuit loses accuracy before it loses current. E4.3's cascode mirrors have almost no slope, and there the same 1 % test reads the knee itself.

XR1 g1 g1 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15
XO1 o1 g1 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15

XR3 g3 g3 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
XO3 o3 g3 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1

Two more errors exist that this lab cannot show. Two transistors drawn alike are never quite alike: their thresholds and current factors differ at random (mismatch). And a wafer is not uniform, so a device far from its partner sees a slightly different process (gradients). Module E7 measures both.

Try it

Run the bench and open Plots: every output current against VO, the five ammeters on one node. Read the 8/1 mirror's lines (_1) first, then compare the other lengths.

Then try four edits. Find the exact copy: iexact_1 reads the 8/1 current at V_out = V_GS. Make M2 a 2:1 copy with m=2 and check that the ratio holds at every VO. Change one length and keep W/L fixed. Finally move I3 to 10 µA and watch V_GS, the copy error and r_out change together.

Check yourself

* a mirror whose output drain is tied to the gate node through VO
.lib sky130 tt
VDD vdd 0 1.8
IREF vdd g 20u
XM1 g g 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
XM2 o g 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
VO o g 0
.control
* sweep the drain from 0.1 V below to 0.1 V above the gate; read it at 0 V offset
dc VO -0.1 0.1 0.01
let iout=-i(VO)
meas dc iout FIND iout AT=0
.endc
.end