Ratios, PMOS mirrors and distributing bias

One reference, many currents

Analog blocks are usually biased from one reference current, which mirrors copy, scale and turn around. The lab builds a small bias tree from a 10 µA reference, with every NMOS and PMOS drawn as W/L = 4/1 µm unit devices.

Ratios. Make an output m units of the reference device and it carries m times the reference current. Use whole units (m=2, or several identical devices), not an odd width. Identical units share every edge effect, so the ratio is a count. A ratio below 1 puts more units on the reference side.

Turning a current around. An NMOS mirror sinks current: its output pulls current toward ground. A PMOS mirror with its sources at VDD sources current into its load. Feed an NMOS sink into a PMOS diode and you get sourced copies of the same reference.

The PMOS side is the tight one in 1.8 V. SKY130's PMOS needs V_SG = 1.255 V for 19.7 µA in two 4/1 units, so P0's gate sits at only 0.545 V. A PMOS output also drifts with its voltage: P2 gives 19.77 µA at 0.3 V, 19.49 µA at 0.9 V and 18.64 µA at 1.5 V. By the module's 1 % definition, its output must stay below 1.167 V.

Why a current travels better than a voltage

A gate voltage sets a current only together with the source voltage under it. If the far block's ground rises by ΔV, its sink's V_GS falls by ΔV. To first order the current falls by g_m·ΔV, a fraction (g_m/I_D)·ΔV of itself. g_m/I_D, from the E2 lesson "Transconductance and gm/ID", is how much current each volt of V_GS buys.

The lab prints g_m/I_D = 12.68 V⁻¹ for N1. Ten millivolts then predicts a 12.7 % drop; the run shows 14.9 %. The rest is the body effect. The far sink's source sits 10 mV above its body, the substrate at ground, and that raises its threshold. The lab prints g_mb/I_D = 2.92 V⁻¹, where g_mb is the transconductance from the body (E3): about 2.9 % more.

The fix is to send a current. The far block receives a current and mirrors it with its own diode device, whose source sits on the far block's ground. Both of its devices see the same ground, so an offset cancels. In the lab the locally mirrored copy moves from 9.95 to 9.93 µA when the far ground rises by 10 mV.

VGR gr 0 10m
XNF nf gn gr 0 sky130_fd_pr__nfet_01v8 W=4 L=1

VGR gr 0 10m
XNL fl fl gr 0 sky130_fd_pr__nfet_01v8 W=4 L=1
XNC nc fl gr 0 sky130_fd_pr__nfet_01v8 W=4 L=1

Biasing the tail of a differential pair

A differential pair is two transistors whose sources share one node, the tail. A mirror output sinks a fixed current from the tail, and the pair splits it between its two drains.

The tail device needs its own V_DS to stay saturated, and the pair stacks its V_GS on top. So the input common-mode voltage must be at least V_GS of the pair device plus the V_DS the tail needs. The plot sweeps VCM.

Read the limit off the plot. To hold the tail within 2.5 % of 20 µA, this pair needs VCM ≥ 1.256 V: 0.789 V for the pair plus 0.467 V for the tail. That is the first number of module E5. E4.3's low-voltage mirrors lower it.

Try it

Run it and read the three groups: the tree at 0.9 V (in1 to iloc), the far ground (gm_id to iloc10) and the tail (itail09 to itail18). Plots shows each sweep.

Then predict before each edit. Change VGR to 5m and check ifar against (g_m/I_D)·ΔV. Make N1 m=4: does it sink four times N1's old current? Lengthen the tail units to L = 2 (W = 8) and watch vcm195 move. Finally route the PMOS gate voltage gp to a PMOS source in the far block whose own VDD sits 10 mV low, and compare its copy with P2's.

Check yourself

* a 1:3 mirror: three reference units, one output unit, output held at V_GS by EO
.lib sky130 tt
VDD vdd 0 1.8
IREF vdd g 10u
XN0 g g 0 0 sky130_fd_pr__nfet_01v8 W=4 L=1 m=3
XN1 o g 0 0 sky130_fd_pr__nfet_01v8 W=4 L=1
* EO copies v(g) onto o without drawing current from g
EO o 0 g 0 1
.control
dc IREF 9u 11u 1u
let iout=-i(EO)
meas dc iout FIND iout AT=10u
.endc
.end