Cascode and wide-swing mirrors

Raise a mirror's output resistance a hundredfold with a cascode, win back the headroom it costs with a wide-swing mirror, and size its bias by measurement where the square-law rule misses.

Lesson
E4.3
Time
30 min
Runs on
ngspice
Check
5 questions

A tail sink needed both a high output resistance and room to swing low, so it was built as the textbook wide-swing cascode mirror, its bias device sized at W/4. In simulation it copied 17.55 µA of a 20 µA reference, 12 % low at every output voltage. The sizing rule assumed the square law.

DC sweepA wide-swing mirror sized by the W/4 ruleOutput current against output voltage. Every device is W/L = 8/1 µm except the 2/1 µm bias device.
05 µA10 µA15 µA20 µA25 µAOutput current00.2 V0.4 V0.6 V0.8 V1.0 V1.2 V1.4 V1.6 V1.8 VOutput voltage VOreference 20 µA17.55 µA at 0.9 V05 µA10 µA15 µA20 µA25 µAOutput current00.5 V1.0 V1.5 VOutput voltage VOreference 20 µA17.55 µA at 0.9 V
  1. Output voltage VO 900 mVi_w4 = 17.55 µA

    At 0.9 V the copy is 17.55 µA: a flat curve, at the wrong current.

  2. Output voltage VO 1.7 Vi_w4 = 17.64 µA

    At 1.7 V it is still only 17.64 µA. A high output resistance holds an error as faithfully as a correct current.

Read the plot as a table
Output voltage VOi_w4
0 V0 A
200 mV16.67 µA
400 mV17.45 µA
600 mV17.5 µA
800 mV17.53 µA
900 mV17.55 µA
1 V17.56 µA
1.2 V17.58 µA
1.4 V17.61 µA
1.6 V17.63 µA
1.7 V17.64 µA
1.8 V17.65 µA

Measured on ngspice 42, SKY130 tt (361 points): mirror w4 of the lab below.

A sizing rule from the square law is a starting point; the copy has to be measured.

A cascode on the mirror

E4.1's simple mirror has rout = ro: 0.80 MΩ at 1.2 V for W/L = 8/1 µm. To raise it, stack a cascode device on the output (E3 lesson "The cascode") and a matching diode on the reference side to bias it.

A stacked cascode mirrorR1 and R2 are diodes stacked in the reference branch; O1 copies R1, and O2 is the cascode on top of it.
A stacked cascode mirrorVDD1.8 VIREF20 µAR28/1R18/1O28/1O18/1outgc1.566 Vgc10.714 Vx0.708 Vout0.900 V
  1. Two diodes stacked

    IREF flows through R2 and R1. R1 sits at VGS = 0.714 V; R2 stacks its own VGS on top, so the cascode gate gc is at 1.566 V.

    20 µA

  2. The cascode holds x

    O2's gate is at gc, so its source x settles one VGS lower: 0.708 V, almost R1's 0.714 V. O1 sees nearly the same voltages as R1 and copies 19.99 µA.

  3. The output moves, x does not

    Raise the output and O2 absorbs the change, so x and O1's current barely move. rout is 102 MΩ at 1.2 V.

    19.99 µA

Read the circuit as text
  • IREF current source (20 µA): + → VDD, − → gc
  • R2 NMOS transistor (8/1): gate → gc, drain → gc, source → gc1
  • R1 NMOS transistor (8/1): gate → gc1, drain → gc1, source → 0
  • O2 NMOS transistor (8/1): gate → gc, drain → out, source → x
  • O1 NMOS transistor (8/1): gate → gc1, drain → x, source → 0
  • out port: terminal → out
  • gc = 1.566 V
  • gc1 = 0.714 V
  • x = 0.708 V
  • out = 0.900 V

Node voltages at Vout = 0.9 V from the lab's mirror c. All bodies are the substrate at ground.

O2 holds O1's drain near R1's, so the copy is accurate: 19.99 µA at 0.9 V, 20.00 µA at 1.7 V. Seen from the output, O2 multiplies O1's ro by its own gain: rout ≈ (gm2 + gmb2)·ro2·ro1. The lab computes that from the device parameters at 1.2 V: 100.8 MΩ against 102.2 MΩ measured, 128 times the simple mirror.

The cost is headroom. R2's VGS is 0.853 V, larger than R1's, because its source sits 0.714 V above its body (the body effect). O2 stays saturated only while Vout > Vx + VDsat ≈ 0.708 + 0.14 = 0.85 V (VDsat: the smallest VDS that keeps a device saturated). Below that, rout collapses: 15.5 MΩ at 0.9 V, 5.39 MΩ at 0.85 V, 2.15 MΩ at 0.8 V.

The current falls slowly, because O1 then acts as a simple mirror. So the 1 % test gives 0.621 V, below the 0.85 V where the cascode stops working.

The wide-swing mirror and the W/4 rule

The stacked mirror wastes headroom: O1 sits at 0.708 V but needs only about 0.14 V. A wide-swing (low-voltage) cascode mirror biases the cascode gate from a separate diode device, so O1 sits just above VDsat and the output can fall to about two VDsat.

The textbook sizes that bias device from the square law. At the same current, a device of width W/4 needs twice the overdrive Vov = VGS − Vth, so its gate sits at Vth + 2Vov. The cascode, of width W, needs Vth + Vov, and its source lands at Vx = Vov, exactly the square law's edge of saturation.

The lab's W/4 mirror does that: Vx = 0.137 V, at O1's simulated VDsat of 0.134 V. Two things go wrong. At 20 µA these devices are in moderate inversion (between weak and strong), where saturation has no sharp edge. And the reference device sits at 0.714 V while O1 sits at 0.137 V, so E4.1's VDS error returns, enlarged.

DC sweepFour 20 µA mirrors against output voltageSimple (i_s), stacked cascode (i_c), wide-swing by the W/4 rule (i_w4), and wide-swing with a reference-side cascode and a W/8 bias device (i_m8).
  • i_s
  • i_c
  • i_w4
  • i_m8
05 µA10 µA15 µA20 µA25 µAOutput current00.2 V0.4 V0.6 V0.8 V1.0 V1.2 V1.4 V1.6 V1.8 VOutput voltage VO20 µAsimple 0.757 Vstacked 0.621 VW/4 0.301 Vmatched W/8 0.297 V05 µA10 µA15 µA20 µA25 µAOutput current00.5 V1.0 V1.5 VOutput voltage VO20 µAsimple 0.757 Vstacked 0.621 VW/4 0.301 Vmatched W/8 0.297 V
  1. Output voltage VO 300 mVi_s = 19.16 µA · i_c = 19.11 µA · i_w4 = 17.37 µA · i_m8 = 19.81 µA

    At 0.3 V the matched W/8 mirror already gives 19.81 µA. The simple and the stacked mirrors give about 19.1 µA, the W/4 mirror 17.4 µA.

  2. Output voltage VO 900 mVi_s = 20.27 µA · i_c = 19.99 µA · i_w4 = 17.55 µA · i_m8 = 20.01 µA

    At 0.9 V: simple 20.27 µA, stacked 19.99 µA, W/4 17.55 µA, matched W/8 20.006 µA.

  3. Output voltage VO 1.7 Vi_s = 21.26 µA · i_c = 20 µA · i_w4 = 17.64 µA · i_m8 = 20.02 µA

    At 1.7 V the simple mirror has climbed to 21.26 µA; the cascodes have hardly moved.

Read the plot as a table
Output voltage VOi_si_ci_w4i_m8
0 V0 A0 A0 A0 A
200 mV18.64 µA18.51 µA16.67 µA19 µA
300 mV19.16 µA19.11 µA17.37 µA19.81 µA
400 mV19.44 µA19.39 µA17.45 µA19.97 µA
600 mV19.82 µA19.76 µA17.5 µA20 µA
800 mV20.13 µA19.97 µA17.53 µA20 µA
900 mV20.27 µA19.99 µA17.55 µA20.01 µA
1 V20.4 µA19.99 µA17.56 µA20.01 µA
1.2 V20.66 µA20 µA17.58 µA20.01 µA
1.4 V20.9 µA20 µA17.61 µA20.02 µA
1.6 V21.14 µA20 µA17.63 µA20.02 µA
1.7 V21.26 µA20 µA17.64 µA20.02 µA
1.8 V21.38 µA20 µA17.65 µA20.03 µA

Measured on ngspice 42, SKY130 tt (361 points). A point marks where each current is 1 % below its value at 0.9 V.

A smaller bias device moves x up: at W/8, Vx = 0.249 V and the copy is 18.96 µA, still 5.2 % low. Sizing alone cannot fix a VDS mismatch.

Match the reference side, then size by measurement

Put a cascode in the reference branch too, on the same bias line, and tie the bottom gates to the top of that branch. Both bottom devices then sit at nearly the same low VDS.

A wide-swing mirror with a reference-side cascodeXB sets the bias line b. R2 and O2 are cascodes on it; R1 and O1 share the gate node g, the top of the reference branch.
A wide-swing mirror with a reference-side cascodeVDDIB20 µAXB1/1VDDIREF20 µAR28/1R18/1O28/1O18/1outb1.014 Vg0.718 Vy0.245 Vx0.246 V
  1. The bias device sets b

    XB is an eighth of the 8 µm width. At 20 µA it needs a larger VGS, so the bias line b sits at 1.014 V.

    20 µA

  2. The cascodes hold y and x low

    R2 and O2 have their gates on b, so their sources sit one VGS lower: y = 0.245 V and x = 0.246 V. Both bottom devices get about 0.25 V, above their 0.137 V VDsat.

  3. The bottom devices match

    R1's gate is tied to g, the top of the reference branch, so g settles where R1 carries 20 µA at y. O1 shares g and sits at nearly the same VDS: it copies 20.006 µA at 0.9 V.

    20.006 µA

  4. Room at the output

    O2 needs only its own VDsat above x, so the output can fall to 0.297 V before the current is 1 % low.

Read the circuit as text
  • IB current source (20 µA): + → VDD, − → b
  • XB NMOS transistor (1/1): gate → b, drain → b, source → 0
  • IREF current source (20 µA): + → VDD, − → g
  • R2 NMOS transistor (8/1): gate → b, drain → g, source → y
  • R1 NMOS transistor (8/1): gate → g, drain → y, source → 0
  • O2 NMOS transistor (8/1): gate → b, drain → n1, source → x
  • O1 NMOS transistor (8/1): gate → g, drain → x, source → 0
  • out port: terminal → n1
  • b = 1.014 V
  • g = 0.718 V
  • y = 0.245 V
  • x = 0.246 V

Node voltages at Vout = 0.9 V from the lab's mirror m8. Widths in µm, all L = 1 µm; all bodies are the substrate at ground.

With the reference matched, the bias width sets only where the bottom devices sit, and so rout and the minimum output voltage.

MirrorIout at 0.9 Vrout at 1.2 VMinimum VoutVx
Simple20.27 µA0.80 MΩ0.757 V(none)
Stacked cascode19.99 µA102 MΩ0.621 V0.708 V
Wide-swing, W/4 bias17.55 µA8.9 MΩ0.301 V0.137 V
Wide-swing, W/8 bias18.96 µA50.1 MΩ0.294 V0.249 V
Matched, W/4 bias20.04 µA5.7 MΩ0.343 V0.129 V
Matched, W/8 bias20.006 µA44.8 MΩ0.297 V0.246 V
Matched, W/12 bias20.004 µA77.9 MΩ0.340 V0.339 V

The lab's i09_*, r12_*, vmin_* and vx09_* lines; Vx at Vout = 0.9 V. All devices L = 1 µm, 8 µm wide except the bias device.

Read the matched rows. At W/4 the bottom devices sit at 0.129 V, in the soft knee: the copy is right, but rout is only 5.7 MΩ. At W/8 they sit at 0.246 V: 44.8 MΩ and the lowest minimum output voltage, 0.297 V. The rule of thumb "two VDsat" gives 0.274 V. At W/12, rout reaches 77.9 MΩ for a minimum of 0.340 V.

DC sweepOutput resistance of the four mirrorsrout = 1/(∂Iout/∂Vout) on a log axis, from the same run.
  • r_s
  • r_c
  • r_w4
  • r_m8
1 kΩ10 kΩ100 kΩ1 MΩ10 MΩ100 MΩ1 GΩOutput resistance00.2 V0.4 V0.6 V0.8 V1.0 V1.2 V1.4 V1.6 V1.8 VOutput voltage VO1 kΩ10 kΩ100 kΩ1 MΩ10 MΩ100 MΩ1 GΩOutput resistance00.5 V1.0 V1.5 VOutput voltage VO
  1. Output voltage VO 400 mVr_s = 434.3 kΩ · r_c = 430.6 kΩ · r_w4 = 2.451 MΩ · r_m8 = 2.261 MΩ

    At 0.4 V the matched W/8 mirror has 2.26 MΩ and climbing; the stacked cascode is no better than the simple mirror.

  2. Output voltage VO 850 mVr_s = 715.1 kΩ · r_c = 5.391 MΩ · r_w4 = 7.341 MΩ · r_m8 = 34.97 MΩ

    At 0.85 V the stacked cascode reaches 5.39 MΩ as O2 saturates; by 1.2 V it passes 100 MΩ.

  3. Output voltage VO 1.2 Vr_s = 800.6 kΩ · r_c = 102.2 MΩ · r_w4 = 8.903 MΩ · r_m8 = 44.77 MΩ

    At 1.2 V: simple 0.80 MΩ, W/4 8.9 MΩ, matched W/8 44.8 MΩ, stacked 102 MΩ.

Read the plot as a table
Output voltage VOr_sr_cr_w4r_m8
0 V4.03 kΩ4.571 kΩ5.727 kΩ5.02 kΩ
200 mV112.4 kΩ93.2 kΩ57.43 kΩ58.62 kΩ
400 mV434.3 kΩ430.6 kΩ2.451 MΩ2.261 MΩ
600 mV602.3 kΩ676.6 kΩ5.39 MΩ20.75 MΩ
800 mV697.5 kΩ2.147 MΩ7.034 MΩ32.87 MΩ
850 mV715.1 kΩ5.391 MΩ7.341 MΩ34.97 MΩ
1 V758.5 kΩ50.67 MΩ8.111 MΩ39.99 MΩ
1.2 V800.6 kΩ102.2 MΩ8.903 MΩ44.77 MΩ
1.4 V830.1 kΩ130 MΩ9.499 MΩ48.08 MΩ
1.6 V847 kΩ147.3 MΩ9.746 MΩ48.09 MΩ
1.8 V844.6 kΩ158.5 MΩ9.124 MΩ38.42 MΩ

Measured on ngspice 42, SKY130 tt (361 points).

The stacked cascode gives the most rout where headroom is plentiful; the matched wide-swing mirror keeps most of it down to about 0.3 V.

Asked in interviews
  1. Draw a cascode current mirror. What are its output resistance and minimum output voltage?

    Two stacked diodes in the reference branch, a cascode device on the output device. rout ≈ (gm + gmb)·ro2, here 102 MΩ against 0.80 MΩ. The output must stay above VGS + VDsat, about 0.85 V here.

  2. What is a wide-swing cascode mirror, and how do you bias it?

    The cascode gates come from a separate, smaller diode device, so the bottom devices sit just above VDsat and the output can fall to about two VDsat. Add a cascode in the reference branch so both bottom devices see the same VDS.

  3. Why might the textbook W/4 sizing fail in a modern process?

    It assumes the square law, which puts Vx exactly at one overdrive, the square-law edge of saturation. In moderate inversion that edge is soft, and without a reference-side cascode the VDS mismatch returns: 17.55 µA instead of 20 µA here.

Try it

Run the bench: seven mirrors, each copying 20 µA, on one output node. Each prints its current at 0.9 V, its rout at 1.2 V, its minimum output voltage and, for the wide-swing ones, Vx. Plots shows every current and rout against VO.

Then size the bias yourself. .param wb=1 sets the bias device of mirror m8; try 2, 1.333, 0.8 and 0.5, and for each read vx09_m8, r12_m8 and vmin_m8. Then delete m8's reference cascode (tie R1's drain to its gate, as in w8) and watch the copy fall back.

SPICEngspice 42 · simulator service
Edit the netlist, then run it
Expected measurements: i09_s = 2.026702e-05 r12_s = 8.005706e+05 vmin_s = 7.567494e-01 i09_c = 1.999103e-05 r12_c = 1.021824e+08 vmin_c = 6.205746e-01 i09_w4 = 1.754715e-05 r12_w4 = 8.903151e+06 vmin_w4 = 3.007557e-01 vx09_w4 = 1.371519e-01 i09_w8 = 1.895962e-05 r12_w8 = 5.011234e+07 vmin_w8 = 2.943730e-01 vx09_w8 = 2.493578e-01 i09_m4 = 2.003817e-05 r12_m4 = 5.715982e+06 vmin_m4 = 3.432707e-01 vx09_m4 = 1.290516e-01 i09_m8 = 2.000553e-05 r12_m8 = 4.476995e+07 vmin_m8 = 2.973674e-01 vx09_m8 = 2.460111e-01 i09_m12 = 2.000356e-05 r12_m12 = 7.794191e+07 vmin_m12 = 3.399127e-01 vx09_m12 = 3.389587e-01 vdsat_m8 = 1.369905e-01 vdsat_w4 = 1.340052e-01 rhand_c = 1.007817e+08

Check yourself

Predict the outputThe matched wide-swing mirror again (bias device W/8), but its output is held at the voltage of g, the top of the reference branch, by a source that draws no current from g. Type the line meas prints, in ngspice's format (for example iout = 2.000553e-05).
* a matched wide-swing mirror with its output held at the reference branch's top node g by EO
.lib sky130 tt
VDD vdd 0 1.8
IREF vdd g 20u
XR2 g b y 0 sky130_fd_pr__nfet_01v8 W=8 L=1
XR1 y g 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
IB vdd b 20u
XB b b 0 0 sky130_fd_pr__nfet_01v8 W=1 L=1
XO2 o b x 0 sky130_fd_pr__nfet_01v8 W=8 L=1
XO1 x g 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
* EO copies v(g) onto the output without loading g
EO o 0 g 0 1
.control
dc IREF 19u 21u 1u
let iout=-i(EO)
meas dc iout FIND iout AT=20u
.endc
.end
ConceptA stacked cascode mirror has VGS = 0.714 V, and its output device needs VDsat = 0.137 V. Below about which output voltage does its output resistance collapse?
ConceptWhy did the W/4 wide-swing mirror copy 17.55 µA instead of 20 µA?
ConceptOn the current plot, which mirror stays within 1 % of its 0.9 V current down to the lowest output voltage?
ConceptIn a wide-swing mirror, which wrong connection leaves the bottom output device with almost no VDS?

Remember

  • A cascode on a mirror raises rout by about (gm + gmb)·ro: 102 MΩ against 0.80 MΩ here, at the cost of VGS + VDsat of headroom (about 0.85 V).
  • A wide-swing mirror biases the cascodes from a separate diode device so the bottom devices sit just above VDsat; its output can fall to about 0.3 V.
  • The square-law W/4 rule leaves the copy 12 % low in SKY130; a reference-side cascode makes both bottom devices see the same VDS and fixes the copy.
  • The bias width trades rout against the minimum output voltage; find it by sweeping, not by the ratio.