Cascode and wide-swing mirrors
Raise a mirror's output resistance a hundredfold with a cascode, win back the headroom it costs with a wide-swing mirror, and size its bias by measurement where the square-law rule misses.
- Lesson
- E4.3
- Time
- 30 min
- Runs on
- ngspice
- Check
- 5 questions
A tail sink needed both a high output resistance and room to swing low, so it was built as the textbook wide-swing cascode mirror, its bias device sized at W/4. In simulation it copied 17.55 µA of a 20 µA reference, 12 % low at every output voltage. The sizing rule assumed the square law.
- Output voltage VO 900 mVi_w4 = 17.55 µA
At 0.9 V the copy is 17.55 µA: a flat curve, at the wrong current.
- Output voltage VO 1.7 Vi_w4 = 17.64 µA
At 1.7 V it is still only 17.64 µA. A high output resistance holds an error as faithfully as a correct current.
Read the plot as a table
| Output voltage VO | i_w4 |
|---|---|
| 0 V | 0 A |
| 200 mV | 16.67 µA |
| 400 mV | 17.45 µA |
| 600 mV | 17.5 µA |
| 800 mV | 17.53 µA |
| 900 mV | 17.55 µA |
| 1 V | 17.56 µA |
| 1.2 V | 17.58 µA |
| 1.4 V | 17.61 µA |
| 1.6 V | 17.63 µA |
| 1.7 V | 17.64 µA |
| 1.8 V | 17.65 µA |
Measured on ngspice 42, SKY130 tt (361 points): mirror w4 of the lab below.
A sizing rule from the square law is a starting point; the copy has to be measured.
A cascode on the mirror
E4.1's simple mirror has rout = ro: 0.80 MΩ at 1.2 V for W/L = 8/1 µm. To raise it, stack a cascode device on the output (E3 lesson "The cascode") and a matching diode on the reference side to bias it.
- Two diodes stacked
IREF flows through R2 and R1. R1 sits at VGS = 0.714 V; R2 stacks its own VGS on top, so the cascode gate gc is at 1.566 V.
20 µA
- The cascode holds x
O2's gate is at gc, so its source x settles one VGS lower: 0.708 V, almost R1's 0.714 V. O1 sees nearly the same voltages as R1 and copies 19.99 µA.
- The output moves, x does not
Raise the output and O2 absorbs the change, so x and O1's current barely move. rout is 102 MΩ at 1.2 V.
19.99 µA
Read the circuit as text
- IREF current source (20 µA): + →
VDD, − →gc - R2 NMOS transistor (8/1): gate →
gc, drain →gc, source →gc1 - R1 NMOS transistor (8/1): gate →
gc1, drain →gc1, source →0 - O2 NMOS transistor (8/1): gate →
gc, drain →out, source →x - O1 NMOS transistor (8/1): gate →
gc1, drain →x, source →0 - out port: terminal →
out
gc= 1.566 Vgc1= 0.714 Vx= 0.708 Vout= 0.900 V
Node voltages at Vout = 0.9 V from the lab's mirror c. All bodies are the substrate at ground.
O2 holds O1's drain near R1's, so the copy is accurate: 19.99 µA at 0.9 V, 20.00 µA at 1.7 V. Seen from the output, O2 multiplies O1's ro by its own gain: rout ≈ (gm2 + gmb2)·ro2·ro1. The lab computes that from the device parameters at 1.2 V: 100.8 MΩ against 102.2 MΩ measured, 128 times the simple mirror.
The cost is headroom. R2's VGS is 0.853 V, larger than R1's, because its source sits 0.714 V above its body (the body effect). O2 stays saturated only while Vout > Vx + VDsat ≈ 0.708 + 0.14 = 0.85 V (VDsat: the smallest VDS that keeps a device saturated). Below that, rout collapses: 15.5 MΩ at 0.9 V, 5.39 MΩ at 0.85 V, 2.15 MΩ at 0.8 V.
The current falls slowly, because O1 then acts as a simple mirror. So the 1 % test gives 0.621 V, below the 0.85 V where the cascode stops working.
The wide-swing mirror and the W/4 rule
The stacked mirror wastes headroom: O1 sits at 0.708 V but needs only about 0.14 V. A wide-swing (low-voltage) cascode mirror biases the cascode gate from a separate diode device, so O1 sits just above VDsat and the output can fall to about two VDsat.
The textbook sizes that bias device from the square law. At the same current, a device of width W/4 needs twice the overdrive Vov = VGS − Vth, so its gate sits at Vth + 2Vov. The cascode, of width W, needs Vth + Vov, and its source lands at Vx = Vov, exactly the square law's edge of saturation.
The lab's W/4 mirror does that: Vx = 0.137 V, at O1's simulated VDsat of 0.134 V. Two things go wrong. At 20 µA these devices are in moderate inversion (between weak and strong), where saturation has no sharp edge. And the reference device sits at 0.714 V while O1 sits at 0.137 V, so E4.1's VDS error returns, enlarged.
- i_s
- i_c
- i_w4
- i_m8
- Output voltage VO 300 mVi_s = 19.16 µA · i_c = 19.11 µA · i_w4 = 17.37 µA · i_m8 = 19.81 µA
At 0.3 V the matched W/8 mirror already gives 19.81 µA. The simple and the stacked mirrors give about 19.1 µA, the W/4 mirror 17.4 µA.
- Output voltage VO 900 mVi_s = 20.27 µA · i_c = 19.99 µA · i_w4 = 17.55 µA · i_m8 = 20.01 µA
At 0.9 V: simple 20.27 µA, stacked 19.99 µA, W/4 17.55 µA, matched W/8 20.006 µA.
- Output voltage VO 1.7 Vi_s = 21.26 µA · i_c = 20 µA · i_w4 = 17.64 µA · i_m8 = 20.02 µA
At 1.7 V the simple mirror has climbed to 21.26 µA; the cascodes have hardly moved.
Read the plot as a table
| Output voltage VO | i_s | i_c | i_w4 | i_m8 |
|---|---|---|---|---|
| 0 V | 0 A | 0 A | 0 A | 0 A |
| 200 mV | 18.64 µA | 18.51 µA | 16.67 µA | 19 µA |
| 300 mV | 19.16 µA | 19.11 µA | 17.37 µA | 19.81 µA |
| 400 mV | 19.44 µA | 19.39 µA | 17.45 µA | 19.97 µA |
| 600 mV | 19.82 µA | 19.76 µA | 17.5 µA | 20 µA |
| 800 mV | 20.13 µA | 19.97 µA | 17.53 µA | 20 µA |
| 900 mV | 20.27 µA | 19.99 µA | 17.55 µA | 20.01 µA |
| 1 V | 20.4 µA | 19.99 µA | 17.56 µA | 20.01 µA |
| 1.2 V | 20.66 µA | 20 µA | 17.58 µA | 20.01 µA |
| 1.4 V | 20.9 µA | 20 µA | 17.61 µA | 20.02 µA |
| 1.6 V | 21.14 µA | 20 µA | 17.63 µA | 20.02 µA |
| 1.7 V | 21.26 µA | 20 µA | 17.64 µA | 20.02 µA |
| 1.8 V | 21.38 µA | 20 µA | 17.65 µA | 20.03 µA |
Measured on ngspice 42, SKY130 tt (361 points). A point marks where each current is 1 % below its value at 0.9 V.
A smaller bias device moves x up: at W/8, Vx = 0.249 V and the copy is 18.96 µA, still 5.2 % low. Sizing alone cannot fix a VDS mismatch.
Match the reference side, then size by measurement
Put a cascode in the reference branch too, on the same bias line, and tie the bottom gates to the top of that branch. Both bottom devices then sit at nearly the same low VDS.
- The bias device sets b
XB is an eighth of the 8 µm width. At 20 µA it needs a larger VGS, so the bias line b sits at 1.014 V.
20 µA
- The cascodes hold y and x low
R2 and O2 have their gates on b, so their sources sit one VGS lower: y = 0.245 V and x = 0.246 V. Both bottom devices get about 0.25 V, above their 0.137 V VDsat.
- The bottom devices match
R1's gate is tied to g, the top of the reference branch, so g settles where R1 carries 20 µA at y. O1 shares g and sits at nearly the same VDS: it copies 20.006 µA at 0.9 V.
20.006 µA
- Room at the output
O2 needs only its own VDsat above x, so the output can fall to 0.297 V before the current is 1 % low.
Read the circuit as text
- IB current source (20 µA): + →
VDD, − →b - XB NMOS transistor (1/1): gate →
b, drain →b, source →0 - IREF current source (20 µA): + →
VDD, − →g - R2 NMOS transistor (8/1): gate →
b, drain →g, source →y - R1 NMOS transistor (8/1): gate →
g, drain →y, source →0 - O2 NMOS transistor (8/1): gate →
b, drain →n1, source →x - O1 NMOS transistor (8/1): gate →
g, drain →x, source →0 - out port: terminal →
n1
b= 1.014 Vg= 0.718 Vy= 0.245 Vx= 0.246 V
Node voltages at Vout = 0.9 V from the lab's mirror m8. Widths in µm, all L = 1 µm; all bodies are the substrate at ground.
With the reference matched, the bias width sets only where the bottom devices sit, and so rout and the minimum output voltage.
| Mirror | Iout at 0.9 V | rout at 1.2 V | Minimum Vout | Vx |
|---|---|---|---|---|
| Simple | 20.27 µA | 0.80 MΩ | 0.757 V | (none) |
| Stacked cascode | 19.99 µA | 102 MΩ | 0.621 V | 0.708 V |
| Wide-swing, W/4 bias | 17.55 µA | 8.9 MΩ | 0.301 V | 0.137 V |
| Wide-swing, W/8 bias | 18.96 µA | 50.1 MΩ | 0.294 V | 0.249 V |
| Matched, W/4 bias | 20.04 µA | 5.7 MΩ | 0.343 V | 0.129 V |
| Matched, W/8 bias | 20.006 µA | 44.8 MΩ | 0.297 V | 0.246 V |
| Matched, W/12 bias | 20.004 µA | 77.9 MΩ | 0.340 V | 0.339 V |
The lab's i09_*, r12_*, vmin_* and vx09_* lines; Vx at Vout = 0.9 V. All devices L = 1 µm, 8 µm wide except the bias device.
Read the matched rows. At W/4 the bottom devices sit at 0.129 V, in the soft knee: the copy is right, but rout is only 5.7 MΩ. At W/8 they sit at 0.246 V: 44.8 MΩ and the lowest minimum output voltage, 0.297 V. The rule of thumb "two VDsat" gives 0.274 V. At W/12, rout reaches 77.9 MΩ for a minimum of 0.340 V.
- r_s
- r_c
- r_w4
- r_m8
- Output voltage VO 400 mVr_s = 434.3 kΩ · r_c = 430.6 kΩ · r_w4 = 2.451 MΩ · r_m8 = 2.261 MΩ
At 0.4 V the matched W/8 mirror has 2.26 MΩ and climbing; the stacked cascode is no better than the simple mirror.
- Output voltage VO 850 mVr_s = 715.1 kΩ · r_c = 5.391 MΩ · r_w4 = 7.341 MΩ · r_m8 = 34.97 MΩ
At 0.85 V the stacked cascode reaches 5.39 MΩ as O2 saturates; by 1.2 V it passes 100 MΩ.
- Output voltage VO 1.2 Vr_s = 800.6 kΩ · r_c = 102.2 MΩ · r_w4 = 8.903 MΩ · r_m8 = 44.77 MΩ
At 1.2 V: simple 0.80 MΩ, W/4 8.9 MΩ, matched W/8 44.8 MΩ, stacked 102 MΩ.
Read the plot as a table
| Output voltage VO | r_s | r_c | r_w4 | r_m8 |
|---|---|---|---|---|
| 0 V | 4.03 kΩ | 4.571 kΩ | 5.727 kΩ | 5.02 kΩ |
| 200 mV | 112.4 kΩ | 93.2 kΩ | 57.43 kΩ | 58.62 kΩ |
| 400 mV | 434.3 kΩ | 430.6 kΩ | 2.451 MΩ | 2.261 MΩ |
| 600 mV | 602.3 kΩ | 676.6 kΩ | 5.39 MΩ | 20.75 MΩ |
| 800 mV | 697.5 kΩ | 2.147 MΩ | 7.034 MΩ | 32.87 MΩ |
| 850 mV | 715.1 kΩ | 5.391 MΩ | 7.341 MΩ | 34.97 MΩ |
| 1 V | 758.5 kΩ | 50.67 MΩ | 8.111 MΩ | 39.99 MΩ |
| 1.2 V | 800.6 kΩ | 102.2 MΩ | 8.903 MΩ | 44.77 MΩ |
| 1.4 V | 830.1 kΩ | 130 MΩ | 9.499 MΩ | 48.08 MΩ |
| 1.6 V | 847 kΩ | 147.3 MΩ | 9.746 MΩ | 48.09 MΩ |
| 1.8 V | 844.6 kΩ | 158.5 MΩ | 9.124 MΩ | 38.42 MΩ |
Measured on ngspice 42, SKY130 tt (361 points).
The stacked cascode gives the most rout where headroom is plentiful; the matched wide-swing mirror keeps most of it down to about 0.3 V.
Asked in interviews
Draw a cascode current mirror. What are its output resistance and minimum output voltage?
Two stacked diodes in the reference branch, a cascode device on the output device. rout ≈ (gm + gmb)·ro2, here 102 MΩ against 0.80 MΩ. The output must stay above VGS + VDsat, about 0.85 V here.
What is a wide-swing cascode mirror, and how do you bias it?
The cascode gates come from a separate, smaller diode device, so the bottom devices sit just above VDsat and the output can fall to about two VDsat. Add a cascode in the reference branch so both bottom devices see the same VDS.
Why might the textbook W/4 sizing fail in a modern process?
It assumes the square law, which puts Vx exactly at one overdrive, the square-law edge of saturation. In moderate inversion that edge is soft, and without a reference-side cascode the VDS mismatch returns: 17.55 µA instead of 20 µA here.
Try it
Run the bench: seven mirrors, each copying 20 µA, on one output node. Each prints its current at 0.9 V, its rout at 1.2 V, its minimum output voltage and, for the wide-swing ones, Vx. Plots shows every current and rout against VO.
Then size the bias yourself. .param wb=1 sets the bias device of mirror m8; try 2, 1.333, 0.8 and 0.5, and for each read vx09_m8, r12_m8 and vmin_m8. Then delete m8's reference cascode (tie R1's drain to its gate, as in w8) and watch the copy fall back.
Run the netlist to draw its plots here.
i09_s = 2.026702e-05 r12_s = 8.005706e+05 vmin_s = 7.567494e-01 i09_c = 1.999103e-05 r12_c = 1.021824e+08 vmin_c = 6.205746e-01 i09_w4 = 1.754715e-05 r12_w4 = 8.903151e+06 vmin_w4 = 3.007557e-01 vx09_w4 = 1.371519e-01 i09_w8 = 1.895962e-05 r12_w8 = 5.011234e+07 vmin_w8 = 2.943730e-01 vx09_w8 = 2.493578e-01 i09_m4 = 2.003817e-05 r12_m4 = 5.715982e+06 vmin_m4 = 3.432707e-01 vx09_m4 = 1.290516e-01 i09_m8 = 2.000553e-05 r12_m8 = 4.476995e+07 vmin_m8 = 2.973674e-01 vx09_m8 = 2.460111e-01 i09_m12 = 2.000356e-05 r12_m12 = 7.794191e+07 vmin_m12 = 3.399127e-01 vx09_m12 = 3.389587e-01 vdsat_m8 = 1.369905e-01 vdsat_w4 = 1.340052e-01 rhand_c = 1.007817e+08Check yourself
Remember
- A cascode on a mirror raises rout by about (gm + gmb)·ro: 102 MΩ against 0.80 MΩ here, at the cost of VGS + VDsat of headroom (about 0.85 V).
- A wide-swing mirror biases the cascodes from a separate diode device so the bottom devices sit just above VDsat; its output can fall to about 0.3 V.
- The square-law W/4 rule leaves the copy 12 % low in SKY130; a reference-side cascode makes both bottom devices see the same VDS and fixes the copy.
- The bias width trades rout against the minimum output voltage; find it by sweeping, not by the ratio.