Start-up: the zero-current state

Two answers to the same equations

The circuit is the beta multiplier of E4.4, a self-biased reference: the circuit sets its own current. A PMOS mirror (XP1, XP2) forces equal currents into XN1 and XN2. XN2 is four times wider, so it needs less gate-source voltage V_GS, and the difference sits across R_S: V_GS1 − V_GS2 = I·R_S.

Step 2 is a second solution of the same equations, the zero-current state. Every self-biased loop has one.

The DC solver returns one answer: it iterates from a guess (E1.2), and from its default guess it lands on the working state. Even a dc sweep of the supply from 0 V, a slow-motion power-up, ends there.

dc VDD 0 1.8 0.01
let i_bare = v(s1)/10k
meas dc idc FIND i_bare AT=1.8

tran 0.05u 40u uic
let i_bare = v(s1)/10k
meas tran ibare FIND i_bare AT=40u

The test that tells the truth is a transient from a dead chip: a PWL supply ramp from 0 V and tran ... uic.

How long it stays off

In this model the zero state does not last forever. Every "off" device leaks a little. At picoamps R_S drops almost nothing, so XN2 passes about four times what XN1 does, and the loop multiplies the leak on each turn. But picoamps charge the gate capacitances slowly.

A start-up time set by leakage is not a design. Leakage moves by decades with temperature and process, and a real chip has leakage paths no model lists, some of which can hold the loop off. The safe statement is the textbook one: a self-biased reference may stay off indefinitely.

A start-up circuit: kick, then step aside

A start-up circuit detects the zero state, pushes current into the loop, then gets out of the way. The schematic's XS1 is a weak pull-up, XS2 the kick and XS3 the off switch. Step through it, then watch the run.

A start-up circuit has three jobs, and each one is a measurement.

XS1 is as long as the library allows, L = 20 µm, to keep that cost small.

Every corner, every ramp, every temperature

One good transient proves little. Run the lab once per corner (.lib sky130 <corner>) and temperature (.temp). In SKY130 the corner named sf has the fast NMOS and the slow PMOS (E2.7).

Now the bare copy after a slow 1 ms ramp, read 50 µs after the ramp ends:

At 27 °C a slow ramp gives leakage time. There the bare reference looks fine in four corners; in ss it is still off. Cold, it is off in every corner. Test only warm and you ship the bug.

Try it

Run it and read the lines in order: the DC sweep's answer, the bare copy after the ramp, the started copy, its time to 90 %, its node voltages, the kick node and the start-up's standing current. Open Plots to see the transient.

Then break it and test it. Change XS3 x a2 0 0 to XS3 x 0 0 0, so the off switch never turns on: the kick stays on and istart rises to about 15 µA. Put the line back. Change the ramp to PWL(0 0 1m 1.8) and the transient to tran 1u 1.05m uic with every AT=40u changed to AT=1.05m. Add .temp -40 and watch ibare stay off. Finally try .lib sky130 ss.

Check yourself

* The bare beta multiplier 40 us into a 10 us power-up ramp
.lib sky130 tt
VDD vdd 0 DC 1.8 PWL(0 0 10u 1.8)
XP1 a b vdd vdd sky130_fd_pr__pfet_01v8 W=4 L=1
XP2 b b vdd vdd sky130_fd_pr__pfet_01v8 W=4 L=1
XN1 a a 0 0 sky130_fd_pr__nfet_01v8 W=2 L=1
XN2 b a s 0 sky130_fd_pr__nfet_01v8 W=8 L=1
RS s 0 10k
.control
tran 0.05u 40u uic
* the reference current in microamps, rounded to a whole number
let iua = floor(v(s)/10k/1u + 0.5)
meas tran iua40 FIND iua AT=40u
.endc
.end