Capstone: a bias block to spec

Turn a bias specification into a circuit with every tool of this module, prove each spec line with one bench run per corner, and hand the block to the differential pair of E5.

Lesson: E4.7
Time: 40 min
Runs on: ngspice
Check: 5 questions

A first try at a bias block copied the E4.4 reference to a 20 µA tail with a simple mirror. It sank 20.51 µA at its 0.9 V test point, but 19.13 µA at 0.3 V and 21.65 µA at 1.5 V. On its first power-up simulation it never started.

DC sweepThe first try: tail current against output voltageThe tail of a simple 2:1 mirror under the E4.4 reference, its output swept from 0 to 1.8 V.

Tail voltage 300 mVtail = 19.13 µA
19.13 µA, 6.7 % below the 0.9 V value: a pair above it loses current at its lowest input.
Tail voltage 900 mVtail = 20.51 µA
The test point: 20.51 µA.
Tail voltage 1.5 Vtail = 21.65 µA
21.65 µA, 5.5 % more: the simple mirror's output resistance is too low (E4.1).

Read the plot as a table

Tail voltage	tail
0 V	0.00001145 fA
200 mV	18.73 µA
300 mV	19.13 µA
400 mV	19.42 µA
600 mV	19.89 µA
800 mV	20.31 µA
900 mV	20.51 µA
1 V	20.71 µA
1.2 V	21.09 µA
1.4 V	21.46 µA
1.5 V	21.65 µA
1.6 V	21.83 µA
1.8 V	22.2 µA

Measured on ngspice 42.

Each fault belongs to one lesson of this module; fixing them starts with a written specification.

The specification

The block feeds a differential pair (E5). Its tail sink sets the pair's current, and its PMOS bias voltage sets the current of the pair's loads and of a second stage. Each line below names the lesson that answers it. The limits were fixed only after the reference solution in the next section had been measured at all five corners, so each one has margin.

Spec line	Limit	Answered by
Tail current, tt, 27 °C, 1.8 V, output at 0.9 V	20 µA ± 5 %	E4.4 (R_S), E4.2 (ratio)
Tail current over every corner, 1.62–1.98 V, −40 to 125 °C	14 µA to 30 µA	E4.6 (temperature)
Tail compliance: current at 0.3 V and at 1.5 V	within 2 % of its 0.9 V value, every condition	E4.3 (wide-swing cascode)
Supply sensitivity at 27 °C: tail at 1.62 V and 1.98 V	within 5 % of its 1.8 V value	E4.4
PMOS bias: an 8/1 PMOS on `pbias`, drain at 0.9 V	10 µA ± 10 % (tt, 27 °C, 1.8 V)	E4.2 (PMOS mirrors)
Start-up: 10 µs ramp at 27 °C and 1 ms ramp at −40 °C	within 1 % of final 50 µs after the ramp ends	E4.5
Block supply current	at most 70 µA, every condition	all

Supply 1.8 V ± 10 %. Corners tt, ss, ff, sf and fs; in SKY130, sf is fast NMOS and slow PMOS (E2.7). The tail band is wide on purpose: the next section explains why.

Why is the tail allowed to move from 14 to 30 µA? The reference is a beta multiplier, a constant-g_m bias. Its current rises with temperature so that the transconductance of the devices it biases stays nearly fixed (E4.6), and the pair's gain and bandwidth follow g_m, not current. A tight current limit would need a different reference, such as a bandgap and a precise resistor, which is beyond this module.

The block

The reference solution is one subcircuit, biasblk vdd tail pbias, with 16 transistors and one resistor. Ground is node 0 inside it. E5 places it with one line, Xbias vdd tail pbias biasblk, and ties the pair's sources to tail. Read it as five pieces, each from one lesson.

The bias block, piece by pieceArrows show where a current or a gate voltage goes. W/L in µm.

Reference and start-up
The beta multiplier of E4.4 sets 10 µA with a res_high_po resistor (W = 0.35 µm, L = 8.54 µm). The start-up of E4.5 kicks it on at power-up and then switches off.
Send currents
PMOS devices on the reference's gate line b copy its current: 10 µA for the NMOS reference stack and 2.5 µA for the cascode bias. Currents travel; gate voltages stay local (E4.2).
Wide-swing cascode
The 2.5 µA diode XBC sets the cascode gate c. The reference stack sets the bottom gate g with its own cascode, so both bottom devices see the same drain voltage (E4.3). The tail is two units of the stack: 20 µA.
PMOS bias output
One more unit on gate g sinks 10 µA from a diode-connected 8/1 PMOS. Its gate is pbias: any 8/1 PMOS with its source at VDD and this gate voltage sources about 10 µA.

Read the diagram as text

Start-up: XS1-XS3: kick at power-up, then off
Reference: Beta multiplier, K = 4, RS a res_high_po: 10 µA
PMOS copies: XP3 4/1: 10 µA; XP4 1/1: 2.5 µA
Cascode bias: XBC 0.5/1.5 diode sets node c
Reference stack: XC1 over XB1, 16/1 units: node g
Tail output: XC2 over XB2, two units: 20 µA
PMOS bias output: XB3 sinks 10 µA from XPB 8/1

Start-up → Reference: kick
Reference → PMOS copies: gate b
PMOS copies → Cascode bias: 2.5 µA
PMOS copies → Reference stack: 10 µA
Cascode bias → Tail output: gate c
Reference stack → Tail output: gate g
Reference stack → PMOS bias output: gate g

The full netlist is the Try it below. Units are whole devices (m=2 for the tail), so the 2:1 ratio does not depend on drawn widths matching.

The tail side: a matched wide-swing cascodeThe two PMOS copies are drawn as current sources. Node voltages at 27 °C with the tail at 0.9 V.

The cascode gate
XBC is a narrow, long diode at 2.5 µA, so its V_GS is large: node c sits at 0.875 V. A cascode device whose gate is at c holds its source about one V_GS lower.
2.5 µA
The reference stack
10 µA flows down through XC1 and XB1. XB1's gate is tied to the top of the stack, node g, so the stack settles where XB1 carries exactly 10 µA. Its drain sits at y = 0.202 V: low, to leave headroom for the cascode above it, but enough to keep XB1 saturated.
10 µA
The tail copies it
XB2 has the same gate voltage g and, through XC2, the same drain voltage: y2 = 0.204 V against y = 0.202 V. Same V_GS, same V_DS, twice the units: 2 × 10 µA. XC2 absorbs any change of the tail voltage, so XB2 hardly sees it.
20 µA

Read the circuit as text

XP3 current source (10 µA): + → VDD, − → g
XP4 current source (2.5 µA): + → VDD, − → c
XC1 NMOS transistor (16/1): gate → c, drain → g, source → y
XB1 NMOS transistor (16/1): gate → g, drain → y, source → 0
XBC NMOS transistor (0.5/1.5): gate → c, drain → c, source → 0
XC2 NMOS transistor (2 × 16/1): gate → c, drain → n1, source → y2
XB2 NMOS transistor (2 × 16/1): gate → g, drain → y2, source → 0
tail port: terminal → n1

g = 0.630 V
c = 0.875 V
y = 0.202 V
y2 = 0.204 V

W/L in µm; NMOS bodies at ground. In the netlist, XP3 and XP4 are 4/1 and 1/1 PMOS on the reference's gate line b.

Proving every line

The bench is one netlist per corner. Three copies of the block hold the tail at 0.3, 0.9 and 1.5 V, so a single sweep reads all three. A dc sweep of VDD gives the nominal values and the supply range. A nested sweep, dc TEMP -40 125 165 VDD 1.62 1.98 0.18, visits the six corners of the supply-temperature box, and MIN/MAX measurements read the worst case. A sweep of the tail voltage gives the minimum output voltage. Two transients test start-up, the second after alter changes the ramp to 1 ms and option temp=-40 makes it cold. One corner runs in about 0.65 s.

Spec line (limit)	tt	ss	ff	sf	fs
Tail, nominal (20 µA ± 5 % in tt)	19.96 µA	22.21 µA	17.93 µA	19.04 µA	20.88 µA
Tail, lowest in the box (≥ 14 µA)	16.13 µA	17.86 µA	14.54 µA	15.21 µA	17.05 µA
Tail, highest in the box (≤ 30 µA)	24.88 µA	27.75 µA	22.35 µA	23.97 µA	25.81 µA
Tail at 0.3 V against 0.9 V (≥ −2 %)	−0.55 %	−0.80 %	−0.39 %	−0.42 %	−0.72 %
Tail at 1.5 V against 0.9 V (≤ +2 %)	+0.09 %	+0.08 %	+0.11 %	+0.12 %	+0.08 %
Tail at 1.62 V and 1.98 V supply (±5 %)	−3.24 / +2.55 %	−3.52 / +2.58 %	−3.10 / +2.55 %	−3.55 / +2.68 %	−3.03 / +2.45 %
PMOS bias output, nominal (10 µA ± 10 % in tt)	10.50 µA	11.58 µA	9.524 µA	10.04 µA	10.98 µA
PMOS bias output, range in the box	8.28–13.28 µA	9.07–14.68 µA	7.53–12.05 µA	7.81–12.81 µA	8.75–13.77 µA
Start-up, 10 µs ramp, 27 °C (within 1 %)	−0.002 %	−0.006 %	−0.001 %	−0.005 %	−0.001 %
Start-up, 1 ms ramp, −40 °C (within 1 %)	0.000 %	0.000 %	0.000 %	0.000 %	0.000 %
Block supply current, nominal / highest (≤ 70 µA)	44.6 / 55.5 µA	49.2 / 61.4 µA	40.5 / 50.4 µA	42.5 / 53.4 µA	46.9 / 57.8 µA
Minimum output voltage, 27 °C (1 % definition)	0.212 V	0.226 V	0.201 V	0.201 V	0.225 V

Five runs of the bench in Try it, one per corner. Every limit holds; the tightest are the ff tail low point (14.54 µA against 14 µA) and the sf supply line (−3.55 % against 5 %).

Notice the corner order of the tail current: ss is highest, ff lowest. That is the constant-g_m reference at work. Slow devices need more current to reach the same g_m, so the reference gives them more.

The worst cases sit at the temperature edges: cold for the lowest tail, hot for the highest tail and the largest supply current (the at= of each line). A sweep in 5 °C steps finds the same extremes, which is why the bench visits only −40 and 125 °C.

DC sweepTail current against tail voltage, three temperaturesOne block in tt at 1.8 V, its tail swept from 0 to 1.8 V at −40, 27 and 125 °C.

−40 °C
27 °C
125 °C

Tail voltage 178 mV−40 °C = 16.54 µA · 27 °C = 19.56 µA · 125 °C = 23.36 µA
Cold, the tail stays within 1 % of its 0.9 V value down to 0.178 V.
Tail voltage 212.5 mV−40 °C = 16.64 µA · 27 °C = 19.76 µA · 125 °C = 23.75 µA
At 27 °C the minimum output voltage is 0.212 V. Compare the first try's simple mirror, whose current had already fallen 6.7 % at 0.3 V.
Tail voltage 264 mV−40 °C = 16.68 µA · 27 °C = 19.89 µA · 125 °C = 24.05 µA
Hot, the knee moves up to 0.264 V, still below the 0.3 V spec point.
Tail voltage 1.5 V−40 °C = 16.72 µA · 27 °C = 19.97 µA · 125 °C = 24.31 µA
Between the knees and 1.8 V every curve is flat: the cascode has raised the output resistance by about the gain of XC2.

Read the plot as a table

Tail voltage	−40 °C	27 °C	125 °C
0 V	-0.0000009169 fA	0.00003257 fA	0.0001141 fA
178 mV	16.54 µA	19.56 µA	23.36 µA
200 mV	16.61 µA	19.7 µA	23.64 µA
212.5 mV	16.64 µA	19.76 µA	23.75 µA
264 mV	16.68 µA	19.89 µA	24.05 µA
400 mV	16.69 µA	19.94 µA	24.27 µA
600 mV	16.7 µA	19.95 µA	24.28 µA
800 mV	16.7 µA	19.95 µA	24.29 µA
1 V	16.71 µA	19.96 µA	24.3 µA
1.2 V	16.71 µA	19.96 µA	24.3 µA
1.4 V	16.72 µA	19.97 µA	24.3 µA
1.5 V	16.72 µA	19.97 µA	24.31 µA
1.6 V	16.72 µA	19.97 µA	24.31 µA
1.8 V	16.73 µA	19.98 µA	24.31 µA

Measured on ngspice 42. Each curve is one dc sweep, with option temp set before it.

This is the number E5 needs. A differential pair's lowest input common-mode voltage is its devices' V_GS plus the tail's minimum output voltage (E4.2). With this tail, the pair loses only about 0.21 V of headroom at 27 °C, and at most 0.264 V hot.

Asked in interviews

Walk me through designing a bias generator for an op-amp.
Write the spec first: currents, compliance of each output, supply and temperature range, start-up, power. Pick a reference (a beta multiplier for constant g_m, a bandgap for constant current) and add start-up. Distribute currents with unit-device mirrors and wide-swing cascodes. Then sweep every corner, supply and temperature, and power it up in a transient.
How do you verify a bias block?
One bench per corner. Sweep supply and temperature with MIN/MAX measurements on each output, and sweep each output voltage for compliance and the minimum output voltage. Then power it up from 0 V with fast and slow ramps, cold, and check the supply current.
How does the bias block limit the op-amp's input common-mode range?
The pair's sources sit on the tail, so the lowest input common mode is the pair's V_GS plus the tail's minimum output voltage. A simple mirror's high knee or a stacked cascode raises it; a wide-swing tail keeps it near two V_Dsat.

Try it

Run it: each line is one row of the spec table for tt. tail_min, tail_max and the others from the box also print where the worst case sat (at= is the temperature of the inner sweep). Then change .lib sky130 tt to each other corner and fill in your own copy of the table.

Now break the block and see which line catches it. Delete the three XS lines: every DC line still passes, but su_fast collapses. Change XC2 and XC1 to L=0.15: watch comp_lo and comp_hi. Set XRS to L=6: the nominal tail leaves its ±5 % band. Make XP4 as wide as XP3: four times the current lifts the cascode gate c, and vmin and comp_lo get worse.

SPICEngspice 42 · simulator service

Edit the netlist, then run it

Expected measurements: tail_nom = 1.995521e-05 pmos_nom = 1.049996e-05 idd_nom = 4.464136e-05 sup_lo = 9.675971e-01 sup_hi = 1.025508e+00 tail_min = 1.613444e-05 at= -4.000000e+01 tail_max = 2.487787e-05 at= 1.250000e+02 comp_lo = 9.944584e-01 at= 1.250000e+02 comp_hi = 1.000905e+00 at= -4.000000e+01 pmos_min = 8.275203e-06 at= -4.000000e+01 pmos_max = 1.328363e-05 at= 1.250000e+02 idd_max = 5.554580e-05 at= 1.250000e+02 vmin = 2.124657e-01 su_fast = 9.999759e-01 tail_end = 1.670733e-05 su_slow = 9.999998e-01

Check yourself

Predict the outputThis is the same block with its three start-up lines deleted. Every DC line of the spec still passes. The netlist powers it up with a 10 µs ramp and prints the tail current at 60 µs in microamps, rounded to a whole number. Type the line (for example tail60 = 2.000000e+01).

* The bias block with its start-up removed, 50 us after a 10 us power-up ramp
.lib sky130 tt
.subckt biasblk vdd tail pbias
* reference (E4.4): beta multiplier, K = 4, R_S is a res_high_po poly resistor
XP1 a b vdd vdd sky130_fd_pr__pfet_01v8 W=4 L=1
XP2 b b vdd vdd sky130_fd_pr__pfet_01v8 W=4 L=1
XN1 a a 0 0 sky130_fd_pr__nfet_01v8 W=2 L=1
XN2 b a s 0 sky130_fd_pr__nfet_01v8 W=8 L=1
XRS s 0 0 sky130_fd_pr__res_high_po W=0.35 L=8.54
* PMOS copies of the reference (E4.2): 10 uA and 2.5 uA
XP3 g b vdd vdd sky130_fd_pr__pfet_01v8 W=4 L=1
XP4 c b vdd vdd sky130_fd_pr__pfet_01v8 W=1 L=1
* wide-swing cascode (E4.3): cascode gate bias, reference stack, tail of two units
XBC c c 0 0 sky130_fd_pr__nfet_01v8 W=0.5 L=1.5
XC1 g c y 0 sky130_fd_pr__nfet_01v8 W=16 L=1
XB1 y g 0 0 sky130_fd_pr__nfet_01v8 W=16 L=1
XC2 tail c y2 0 sky130_fd_pr__nfet_01v8 W=16 L=1 m=2
XB2 y2 g 0 0 sky130_fd_pr__nfet_01v8 W=16 L=1 m=2
* PMOS bias output: one unit sinks 10 uA from an 8/1 PMOS diode
XB3 pbias g 0 0 sky130_fd_pr__nfet_01v8 W=16 L=1
XPB pbias pbias vdd vdd sky130_fd_pr__pfet_01v8 W=8 L=1
.ends biasblk
VDD vdd 0 DC 1.8 PWL(0 0 10u 1.8)
X1 vdd t pb biasblk
VT t 0 0.9
.control
tran 0.1u 60u uic
* the tail current in microamps, rounded to a whole number
let tail_ua = floor(-i(VT)/1u + 0.5)
meas tran tail60 FIND tail_ua AT=60u
.endc
.end

ConceptIn the spec table, the tail current is highest in the ss corner and lowest in ff. Why?

In ss the PMOS copies are slow, so they copy more current than they shouldIn ff the cascode leaves saturation and takes current away from the tailThe reference holds g_m nearly constant, and slow devices need more current for the same g_mIn ss the resistor R_S is lower too, so the same ΔV_GS drives more current through it

ConceptRead the compliance plot. At which tail voltage, at 125 °C, has the tail current fallen 1 % below its 0.9 V value?

0.212 V0.3 V0.178 V0.264 V

ConceptA pair whose devices need V_GS = 0.75 V sits on this tail at 27 °C. About what is its lowest input common-mode voltage?

0.96 V1.05 V0.75 V1.5 V

ConceptWhich spec line is answered by the reference-side cascode XC1, the device that makes this a matched wide-swing mirror?

Start-up within 1 % 50 µs after the rampTail at 0.3 V and at 1.5 V within 2 % of its 0.9 V valueTail at 1.62 V and 1.98 V supply within 5 % of its 1.8 V valueBlock supply current at most 70 µA

Remember

Write the bias spec as lines, each with a limit and a measurement, and set the limits only after a reference solution is measured at every corner.
One bench per corner: a supply sweep for nominal and sensitivity, a nested TEMP × VDD sweep with MIN/MAX for the worst case, an output sweep for compliance, and power-up transients, fast and cold-slow.
A matched wide-swing cascode tail holds within 1 % down to about 0.21 V here; the pair's lowest input common mode is its V_GS plus that.
A constant-g_m reference moves its current with temperature and corner on purpose; specify the tail as a band and let g_m carry the accuracy.