• RTL Design48 lessons

Write combinational and clocked logic, simulate your design, and inspect the gates it becomes.

• SystemVerilog49 lessons
• Protocols51 lessons
• UVM61 lessons
• Assertions14 lessons
• Functional Coverage8 lessons
• DPI and Foreign Models10 lessons

Build testbenches, check bus protocols, and use assertions and coverage to find what you missed.

• Physical Design47 lessons

Constrain timing, place cells, build a clock tree and route a SKY130 block with OpenROAD.

• Analog Circuit Foundations51 lessons

Analog circuit design, SPICE simulation, and the boundary where continuous signals meet digital logic.

Questions and answers linked to the lessons. Available soon.

Questions and answers linked to the lessons. Available soon.

Questions and answers linked to the lessons. Available soon.

Questions and answers linked to the lessons. Available soon.