The differential pair

Build a differential pair, watch it split a fixed tail current between two transistors, measure how far the input can move before one side takes it all, and read its gain from the half circuit.

Lesson: E5.1
Time: 30 min
Runs on: ngspice
Check: 5 questions

A sensor front end had to amplify a 2 mV, 1 kHz signal riding on 200 mV of 50 Hz hum, the same on both wires. A single-transistor stage amplified both, and the hum drove its output from rail to rail.

TransientThe same input into one transistor and into a pairTop: one transistor (W/L = 10/1 µm, 50 kΩ load). Bottom: a pair of the same transistors, read as v(d2) − v(d1).

v(dcs)
vod

Time 5.25 msv(dcs) = 59.41 mV · vod = 16.67 mV
The hum is near its top: the single stage is hard on and its drain sits at the ground rail. The pair shows a clean +16.7 mV peak of the signal.
Time 14.75 msv(dcs) = 1.794 V · vod = -16.12 mV
Half a hum period later the single stage is cut off, near 1.8 V. The pair ignores the hum, which moved both its gates together.

Read the plot as a table

Time	v(dcs)	vod
0 s	1.333 V	-0.8882 fV
5 ms	59.84 mV	-385.7 nV
5.25 ms	59.41 mV	16.67 mV
10 ms	1.333 V	418.6 nV
14.75 ms	1.794 V	-16.12 mV
15 ms	1.794 V	433.6 nV
20 ms	1.333 V	-29.48 nV

Measured on ngspice 42 (1000 of the run's 2008 time points).

The fix was two transistors sharing one current, which answer the difference between two wires and largely ignore what the wires share.

A differential pair with resistor loadsM1 and M2 share the tail; M5 copies IB through the diode MB.

The tail sets the total
MB turns IB into a gate voltage; M5 copies it and pulls 19.56 µA out of the tail, whatever the gates do.
19.56 µA
Balance
With both gates at 1.2 V, v_d = 0 and each identical half carries 9.78 µA, so both drains sit at 1.311 V.
9.78 µA · 9.78 µA
Steering
Raise in+ by 25 mV and lower in− by 25 mV, so v_d = +50 mV. M1 carries 13.73 µA, M2 5.83 µA, and the sum barely moves.
13.73 µA · 5.83 µA

Read the circuit as text

RD1 resistor (50 kΩ): pin 1 → VDD, pin 2 → d1
RD2 resistor (50 kΩ): pin 1 → VDD, pin 2 → d2
M1 NMOS transistor (10/1): gate → n1, drain → d1, source → tail
M2 NMOS transistor (10/1): gate → n2, drain → d2, source → tail
IB current source (20 µA): + → VDD, − → n3
MB NMOS transistor (8/1): gate → n3, drain → n3, source → 0
M5 NMOS transistor (8/1): gate → n3, drain → tail, source → 0
in+ port: terminal → n1
in− port: terminal → n2

d1 = 1.311 V
d2 = 1.311 V
tail = 0.454 V

Operating point of the lab at v_d = 0. NMOS bodies at ground. W/L in µm.

Two matched NMOS transistors, M1 and M2, join their sources at the tail. A current source, here the mirror device M5 (E4.1 The simple mirror and its errors), pulls a fixed current I_SS out of it.

M5's gate line, nb, comes from an ideal 20 µA source IB into the diode MB, and the whole module keeps that bias. On a chip, nb would come from a bias block like the one in E4.7 Capstone: a bias block to spec.

The differential input v_d = v_in+ − v_in− is the difference of the gate voltages. The common-mode input V_CM is their average, 1.2 V here. The lab sweeps v_d and keeps V_CM fixed.

DC sweepThe tail current splits between M1 and M2Pair A (W/L = 10/1 µm); each current is read by a 0 V source in series with its load.

I_D1
I_D2
I_D1 + I_D2

Differential input v_d -300 mVI_D1 = 25.78 nA · I_D2 = 19.69 µA · I_D1 + I_D2 = 19.72 µA
M2's gate is 300 mV above M1's, so M2 carries almost all of the tail current.
Differential input v_d 0 VI_D1 = 9.778 µA · I_D2 = 9.778 µA · I_D1 + I_D2 = 19.56 µA
Balance: each side carries 9.78 µA, half of the 19.56 µA tail.
Differential input v_d 120.2 mVI_D1 = 17.63 µA · I_D2 = 1.959 µA · I_D1 + I_D2 = 19.59 µA
At v_d = +120.2 mV, M1 carries 90 % of the total and M2 10 %.
Differential input v_d 300 mVI_D1 = 19.69 µA · I_D2 = 25.78 nA · I_D1 + I_D2 = 19.72 µA
At +300 mV M2 is down to 25.8 nA, because M1 already has all the current there is.

Read the plot as a table

Differential input v_d	I_D1	I_D2	I_D1 + I_D2
-400 mV	1.509 nA	19.79 µA	19.79 µA
-300 mV	25.78 nA	19.69 µA	19.72 µA
-200 mV	349.7 nA	19.29 µA	19.64 µA
0 V	9.778 µA	9.778 µA	19.56 µA
120.2 mV	17.63 µA	1.959 µA	19.59 µA
200 mV	19.29 µA	349.7 nA	19.64 µA
300 mV	19.69 µA	25.78 nA	19.72 µA
400 mV	19.79 µA	1.509 nA	19.79 µA

Measured on ngspice 42 (the lab, 1001 points). The sum rises from 19.56 to 19.72 µA at +300 mV: the tail node moves, and M5 is not ideal.

The two drain currents always add up to the tail current. A small v_d moves current from one side to the other, and a large one sends all of it to one side: the pair steers the current.

So the pair never delivers more than I_SS. That ceiling sets an op-amp's slew rate (E5.6).

How far the input can move

Between balance and full steering lies the linear range. Mark it where one side carries 90 %. Two laws predict that point from g_m/I_D, one device's transconductance per unit current at balance (E2.5 Transconductance and g_m/I_D).

Square law (strong inversion)
I_D = (k/2)V_ov² with overdrive V_ov, so g_m/I_D = 2/V_ov. The difference current is ΔI = (I_SS/2)·x·√(4 − x²), x = v_d/V_ov. ΔI = 0.8 I_SS at x = 0.894: v_d,90 = 1.789/(g_m/I_D). Full steering at √2·V_ov.
Exponential law (weak inversion)
Below threshold the current is exponential in V_GS, and ΔI = I_SS·tanh(v_d·(g_m/I_D)/2). So v_d,90 = ln 9/(g_m/I_D) = 2.197/(g_m/I_D).

The lab holds a second pair, B, of W/L = 1/1 µm on its own tail. The same current through a narrower device needs more overdrive, so its g_m/I_D is lower.

DC sweepA narrow pair stays linear over a wider inputShare of each pair's current in M1.

pair A, 10/1
pair B, 1/1

Differential input v_d 120.2 mVpair A, 10/1 = 90% · pair B, 1/1 = 68.94%
Pair A reaches 90 % at v_d = 120.2 mV, while pair B is still far from it.
Differential input v_d 284.3 mVpair A, 10/1 = 99.8% · pair B, 1/1 = 90%
Pair B needs 284.3 mV: more than twice the range, from the same current.

Read the plot as a table

Differential input v_d	pair A, 10/1	pair B, 1/1
-400 mV	0.007625%	2.267%
-200 mV	1.78%	19.73%
0 V	50%	50%
120.2 mV	90%	68.94%
200 mV	98.22%	80.27%
284.3 mV	99.8%	90%
400 mV	99.99%	97.73%

Measured on ngspice 42 (the lab, 1001 points).

Pair	g_m/I_D at balance	Square law, v_d,90	Exponential law, v_d,90	Measured v_d,90
A, 10/1 µm	17.61 /V	101.6 mV	124.7 mV	120.2 mV
B, 1/1 µm	6.69 /V	267.5 mV	328.6 mV	284.3 mV

Both laws use M1's measured g_m/I_D; the lab prints every number.

Pair A, at 17.6 /V, is in moderate inversion (between weak and strong, E2.5) and lands near the exponential law. Pair B, in strong inversion, lands 6 % wide of the square law. The laws tell you which way to move; the simulator tells you how far.

The trade is the one from E2.5: a wide device gives more g_m per µA and a narrower linear range, a narrow one the reverse.

The tail stands still: the half circuit

For a small v_d, one side gains what the other loses, so the tail has no reason to move; the figure checks that.

DC sweepDifferential output and tail voltagePair A: differential output above, tail node below.

v(d2) − v(d1)
v(taila)

Differential input v_d 0 Vv(d2) − v(d1) = -2.211 pV · v(taila) = 454.2 mV
At balance the slope is 8.238 V/V, the differential gain. The tail is flat at 0.454 V.
Differential input v_d 300 mVv(d2) − v(d1) = 983.3 mV · v(taila) = 540.4 mV
All the current runs through M1 and the output stops at I_SS·R_D. The tail now follows the higher gate.

Read the plot as a table

Differential input v_d	v(d2) − v(d1)	v(taila)
-400 mV	-989.4 mV	581.8 mV
-200 mV	-947.2 mV	499.9 mV
0 V	-2.211 pV	454.2 mV
200 mV	947.2 mV	499.9 mV
300 mV	983.3 mV	540.4 mV
400 mV	989.4 mV	581.8 mV

Measured on ngspice 42 (the lab, 1001 points).

A node that does not move for the signal is an AC ground. Cut the circuit down the middle and ground the tail, and each half is a common-source stage (E3.2 Common source with a resistor load) driven by ±v_d/2.

Each drain moves by ∓g_mR_D·v_d/2, so A_d = g_mR_D, or g_m(R_D ∥ r_o) with the device's output resistance. M1's operating point gives 8.248; the run's slope is 8.238.

For a common-mode input both sides push the same way, so the tail moves. E5.2 measures what that does.

One transistor

* gate = 0.6455 V + hum + signal
VGC gc0 0 0.6455
VHC gh gc0 SIN(0 0.2 50)
ES gc gh sig 0 1
RDC vdd dcs 50k
XMC dcs gc 0 0 sky130_fd_pr__nfet_01v8 W=10 L=1

cs_min = 5.937513e-02, cs_max = 1.794010e+00: the hum drives the drain from rail to rail.

A pair

* both gates = 1.2 V + hum, signal split between them
VH cm cm0 SIN(0 0.2 50)
EP inp cm sig 0 0.5
EN inn cm sig 0 -0.5
XM1 d1 inp tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
XM2 d2 inn tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1

od_max = 1.667884e-02: v(d2) − v(d1) carries 8.3 × 2 mV of signal and rejects the hum.

Both from the hook's netlist on ngspice 42.

Asked in interviews

Why use a differential pair instead of one transistor?
It amplifies the difference between two inputs and rejects what they share: hum, supply noise, a drifting bias. The tail current also caps how far any input can push it.
What sets the input range over which the pair is linear?
The g_m/I_D of the pair devices sets it. The square law steers all current at √2 V_ov, and in weak inversion 90 % is reached at ln 9/(g_m/I_D). Narrower devices or more current widen the range and cost gain per µA.
What is the small-signal gain of a resistively loaded pair?
Differentially it is g_m(R_D ∥ r_o), with g_m of one device at I_SS/2, because the tail is an AC ground and each half is a common-source stage. Taken from one drain, the gain is half of that.

Try it

Run the netlist. a90 and b90 are the differential inputs at which M1 carries 90 % of each pair's current; sq90_* and ex90_* are the two laws' predictions from the measured g_m/I_D. ad0 is the slope of v(d2) − v(d1) at balance, and ad_hand is g_m(R_D ∥ r_o) from the operating point.

Predict, then run. Halve the width of pair A (W=5): g_m/I_D falls, so a90 should grow and ad0 should shrink. Then set IB to 40u and the four 50k loads to 25k (40 µA through 50 kΩ would need 2 V): twice the current through the same devices moves both pairs toward strong inversion, and a90 and b90 grow. Last, change VCM to 0.9 and watch pair B: its tail runs out of headroom (E5.2).

SPICEngspice 42 · simulator service

Edit the netlist, then run it

Expected measurements: id1_0 = 9.777543e-06 isum_0 = 1.955509e-05 a90 = 1.202120e-01 b90 = 2.843037e-01 ad0 = 8.237701e+00 ad_hand = 8.248154e+00

Check yourself

Predict the outputThis is a pair reduced to its model: two G sources of 1 mS (one per side), 10 kΩ loads and a 50 kΩ tail resistance. The inputs carry +0.5 V and −0.5 V of AC. The run prints the real part of v(d2) − v(d1). Type the line meas prints (format: ad = 6.319360e-01).

* a differential pair as a model: g_m = 1 mS per side, R_D = 10 k, a 50 k tail
VP g1 0 dc 0 ac 0.5
VN g2 0 dc 0 ac -0.5
G1 d1 s g1 s 1m
G2 d2 s g2 s 1m
RD1 d1 0 10k
RD2 d2 0 10k
RSS s 0 50k
.control
ac lin 3 1k 3k
let ad=real(v(d2)-v(d1))
meas ac ad FIND ad AT=1k
.endc
.end

ConceptRead the current-split plot of pair A. At what differential input does M2 carry 10 % of the tail current?

v_d = −120 mVv_d = +300 mVv_d = +120 mVv_d = +55 mV

ConceptFour half circuits are drawn for a resistor-loaded pair with a tail resistance R_SS. Which one is wrong?

Common-mode input with an ideal tail current source: the source sees an open circuit and the gain is 0Common-mode input: each half has 2R_SS from its source to groundDifferential input: the tail is grounded, and each half is a common-source stage driven by ±v_d/2Common-mode input: the tail is grounded, so each half has gain −g_mR_D

ConceptAt the same tail current, which change widens the range of v_d over which the pair stays linear?

Make both input devices narrower, to lower their g_m/I_DRaise the common-mode input, so the tail has more headroomMake both input devices wider, to raise their g_mRaise the load resistors, so each drain moves further

ConceptPair A (19.56 µA tail) gets a 1 V differential input. What do the drain currents do?

M1 carries about twice the tail current, because its V_GS rose by 0.5 VM1 carries the whole tail current and M2 is off; more v_d changes nothingBoth turn off, because the tail rises above the lower gateThey stay near balance, because the tail current source holds each at I_SS/2

Remember

A differential pair is two matched transistors sharing a tail current; the drain currents always add up to I_SS, and the differential input decides the split.
The pair steers: past a few hundred millivolts one side carries all of I_SS, so it can never deliver more than the tail current.
The linear range scales with 1/(g_m/I_D): 90 % steering at 120 mV for g_m/I_D = 17.6 /V and at 284 mV for 6.7 /V; the square and exponential laws bracket the run.
For a differential signal the tail is an AC ground, so each half is a common-source stage and A_d = g_m(R_D ∥ r_o).

Two transistors share one current

How far the input can move

The tail stands still: the half circuit

Try it

Check yourself

Remember