Common mode: rejection and the input range

Drive both inputs of an OTA together, measure how much still reaches the output and why, and find the input levels at which every transistor stays in saturation.

Lesson: E5.2
Time: 30 min
Runs on: ngspice
Check: 5 questions

An op-amp buffer in a data converter's reference path was right at 0.9 V and 61 mV low at 1.4 V. Its datasheet's input common-mode range ended below 1.3 V. Above it, one input transistor left saturation and the output stopped following.

DC sweepA unity-gain buffer's error against its input levelv_out − v_in of OTA-A wired as a follower, as the input sweeps from 0 to 1.8 V.

Input V_CM 900 mVv(out) − v(in) = -2.166 mV
At 0.9 V the buffer is 2.17 mV low: that is its offset (E5.4).
Input V_CM 1.27 Vv(out) − v(in) = -10.51 mV
Near 1.265 V the error passes 10 mV and grows fast.
Input V_CM 1.4 Vv(out) − v(in) = -60.92 mV
At 1.4 V the output is 60.9 mV below the input.

Read the plot as a table

Input V_CM	v(out) − v(in)
0 V	66.04 mV
200 mV	8.4 mV
400 mV	4.652 mV
600 mV	982.8 µV
800 mV	-1.279 mV
900 mV	-2.166 mV
1 V	-3.114 mV
1.2 V	-6.221 mV
1.27 V	-10.51 mV
1.4 V	-60.92 mV
1.6 V	-231 mV
1.8 V	-424.5 mV

Measured on ngspice 42 (181 points, 10 mV apart).

One tail transistor sets two datasheet lines: how well the amplifier ignores what its inputs share, and the input levels at which it works at all.

Both inputs move together

This lesson uses OTA-A, the five-transistor OTA that E5.3 builds: the pair of E5.1 with a PMOS current mirror (E4.2 Ratios, PMOS mirrors and distributing bias) as its load. M1's gate is the + input and M2's gate the − input; the mirror turns the two drain currents into one output.

OTA-A with one source on both inputsThe common-mode bench: the same voltage drives M1 and M2.

Both gates rise
VCM lifts both gates by the same small amount. Each half sees the same change, so the tail node rises with them and the split stays half and half.
The tail current changes a little
M5 is a transistor, with an output resistance R_SS = 119.2 kΩ. As the tail rises, M5 passes slightly more current, and both halves share the increase.
I_SS + ΔI
The mirror cancels most of it
M1's extra current flows through M3 and is copied by M4 into the output, where M2 takes out its own equal share. Only the mismatch between the two reaches C_L.

Read the circuit as text

M3 PMOS transistor (8/1): gate → x, source → VDD, drain → x
M4 PMOS transistor (8/1): gate → x, source → VDD, drain → out
M1 NMOS transistor (10/1): gate → n1, drain → x, source → tail
M2 NMOS transistor (10/1): gate → n1, drain → out, source → tail
IB current source (20 µA): + → VDD, − → n2
MB NMOS transistor (8/1): gate → n2, drain → n2, source → 0
M5 NMOS transistor (8/1): gate → n2, drain → tail, source → 0
C_L capacitor (1 pF): pin 1 → out, pin 2 → 0
out port: terminal → out
VCM voltage source (0.9 V + ac): + → n1, − → 0

x = 0.618 V
out = 0.898 V
tail = 0.204 V

Operating point of the lab at 0.9 V. NMOS bodies at ground, PMOS bodies at VDD. W/L in µm.

The common-mode gain A_cm is the output change per volt applied to both inputs at once. The common-mode rejection ratio CMRR = A_d/A_cm compares it with the differential gain A_d; in decibels it is the difference of the two gains.

The lab measures both on copies of OTA-A. A 1 TH inductor from the output to the − input holds each copy at its unity-gain DC point, and a 1 F capacitor sets that input for AC. One copy gets AC on + only (A_d), another the same AC on both inputs (A_cm).

AC analysisDifferential gain and three common-mode gainsA_d of OTA-A, and A_cm as built, with an ideal tail, and with the output held at the level of node x.

A_d
A_cm as built
A_cm, ideal tail
A_cm, out at V_x

Frequency 10 HzA_d = 42.71 dB · A_cm as built = -12.66 dB · A_cm, ideal tail = -14.6 dB · A_cm, out at V_x = -28.44 dB
At 10 Hz: A_d = 42.71 dB, A_cm = −12.66 dB, so CMRR = 55.37 dB. An ideal tail barely helps (−14.60 dB). Holding the output at V_x does: −28.44 dB.
Frequency 1 MHzA_d = 28.04 dB · A_cm as built = -27.3 dB · A_cm, ideal tail = -29.27 dB · A_cm, out at V_x = -41.15 dB
At 1 MHz both gains have fallen by the same output pole, so the CMRR is still 55.35 dB.

Read the plot as a table

Frequency	A_d	A_cm as built	A_cm, ideal tail	A_cm, out at V_x
1 Hz	42.71 dB	-12.66 dB	-14.6 dB	-28.44 dB
10 Hz	42.71 dB	-12.66 dB	-14.6 dB	-28.44 dB
100 Hz	42.71 dB	-12.66 dB	-14.6 dB	-28.44 dB
1 kHz	42.71 dB	-12.66 dB	-14.6 dB	-28.44 dB
10 kHz	42.7 dB	-12.67 dB	-14.61 dB	-28.44 dB
100 kHz	41.63 dB	-13.74 dB	-15.68 dB	-29.24 dB
1 MHz	28.04 dB	-27.3 dB	-29.27 dB	-41.15 dB
10 MHz	8.185 dB	-45.35 dB	-49.02 dB	-49.62 dB
100 MHz	-12.57 dB	-47.74 dB	-62.52 dB	-47.91 dB

Measured on ngspice 42 (the lab netlist, 20 points per decade).

What sets the common-mode gain

The textbook result for this OTA is |A_cm| ≈ 1/(2g_m3R_SS), where R_SS is the tail's output resistance. With g_m3 = 93.63 µS and R_SS = 119.2 kΩ that is −26.97 dB. The run gives −12.66 dB, five times more common-mode gain.

Bench	A_cm at 10 Hz	What it tests
OTA-A as built, output at 0.898 V	−12.66 dB	the real circuit
Ideal tail current source	−14.60 dB	R_SS → ∞
Output held at 0.620 V, beside V_x = 0.618 V	−28.44 dB	both halves symmetric
Hand formula 1/(2g_m3R_SS)	−26.97 dB	assumes symmetry

All four from the lab netlist on ngspice 42.

The formula assumes the two halves are mirror images. They are not: M1's drain sits at the diode node x (0.618 V) and M2's at the output (0.898 V). With the tail at 0.204 V, M2 has 0.28 V more across it, and its output conductance differs from M1's (0.90 µS against 1.18 µS).

When the inputs rise, the tail rises and both drain-source voltages shrink. The two devices lose different amounts of current, and the high-resistance output turns that small difference into a large voltage. An ideal tail does not remove it; equal drain voltages do.

The arithmetic, from the lab's operating point: the tail follows the inputs at 0.80 V per volt (below 1 because of body effect). M1 loses g_ds1 and M2 loses g_ds2 of current per volt of tail rise, and the mirror passes M1's loss to the output. The output node is short of (g_ds1 − g_ds2) × 0.80 per volt of input, which across its g_ds2 + g_ds4 gives 0.187 V/V. Add the textbook tail term 1/(2g_m3R_SS) = 0.045, and the total, 0.232 or −12.70 dB, lands on the run's −12.66 dB.

So in this OTA the asymmetry, not the tail, sets the CMRR. The same asymmetry causes its systematic offset (E5.4). A better tail only pays once the two drains match.

AC on one input

VPD pd 0 DC 0.9 AC 1
XD pd nd od vdd ota
LD od nd 1T
CD nd 0 1

ad10 = 4.271332e+01: the differential gain, not a common-mode number.

The same AC on both inputs

VPC pc 0 DC 0.9 AC 1
VFC fc 0 DC 0 AC 1
XC pc nc oc vdd ota
LC oc nc 1T
CC nc fc 1

acm10 = -1.265539e+01, so cmrr10 = 5.536871e+01 dB.

Both in the lab netlist. A bench that drives one input measures A_d, however it is labelled.

The input common-mode range

The input common-mode range (ICMR) is the span of input levels over which every transistor stays in saturation. Each edge belongs to one device.

Lower edge: the tail
M5 needs V_DS5 ≥ V_Dsat5. The tail sits V_GS1 below the inputs, so V_CM ≥ V_GS1 + V_Dsat5 = 0.696 + 0.134 = 0.830 V, with the 0.9 V values.
Upper edge: the input device
M1's drain is held at VDD − V_SG3, and M1 leaves saturation when that falls below V_CM − V_th1. So V_CM ≤ VDD − V_SG3 + V_th1 = 1.8 − 1.182 + 0.637 = 1.255 V.

V_SG3 is large because SKY130's PMOS threshold is large: |V_th3| = 1.029 V at L = 1 µm (E2.2 Threshold and the regions). That is why the upper edge sits so low on a 1.8 V supply.

The run tracks both margins, V_DS − V_Dsat of M5 and of M1, across a sweep of a follower. It also extracts the open-loop gain at every input level from a second follower with 1 mV in its feedback path: the loop leaves 1/(1 + A) of that 1 mV, which gives A.

DC sweepOpen-loop gain and tail current across the input rangeGain from the two-follower bench (above) and M5's drain current on a log axis (below), with the measured saturation edges.

open-loop gain
tail current

Input V_CM 300 mVopen-loop gain = 40.34 dB · tail current = 5.149 nA
At 0.3 V the tail carries 5.1 nA, yet the DC gain still reads 40.3 dB and a follower would be only 6.3 mV off. Nothing at DC warns you.
Input V_CM 810.6 mVopen-loop gain = 42.85 dB · tail current = 17.44 µA
M5 leaves saturation at 0.811 V; the hand estimate was 0.830 V. Below this the tail current falls by decades.
Input V_CM 900 mVopen-loop gain = 42.73 dB · tail current = 18.67 µA
Mid-range: 42.73 dB and 18.67 µA.
Input V_CM 1.274 Vopen-loop gain = 41.26 dB · tail current = 19.66 µA
M1 leaves saturation at 1.274 V; the hand estimate was 1.255 V. Body effect has raised V_th1 from 0.637 V to 0.702 V here, because the tail rose with the inputs while M1's body stayed at ground.
Input V_CM 1.4 Vopen-loop gain = 39.43 dB · tail current = 19.77 µA
Above the edge the gain sags to 39.4 dB and the follower's error grows to 60.9 mV.

Read the plot as a table

Input V_CM	open-loop gain	tail current
0 V	18.85 dB	4.168 pA
200 mV	38.43 dB	353.3 pA
300 mV	40.34 dB	5.149 nA
400 mV	40.89 dB	69.88 nA
600 mV	42.39 dB	4.478 µA
800 mV	42.86 dB	17.14 µA
810.6 mV	42.85 dB	17.44 µA
900 mV	42.73 dB	18.67 µA
1 V	42.55 dB	19.11 µA
1.2 V	41.89 dB	19.54 µA
1.274 V	41.26 dB	19.66 µA
1.4 V	39.43 dB	19.77 µA
1.6 V	38.7 dB	19.82 µA
1.8 V	38.64 dB	19.82 µA

Measured on ngspice 42 (the range netlist, 181 points).

The upper edge shows up in every test. The lower edge hides: the gain of a transistor pair depends on g_m/I_D and r_o·I_D, which hold up as the current falls, so a starved OTA keeps its DC gain. What it loses is speed, because its unity-gain frequency g_m/(2πC_L) falls with the current.

Asked in interviews

Define CMRR.
The ratio of differential gain to common-mode gain, A_d/A_cm, usually in dB. It says how much better the amplifier responds to the difference between its inputs than to what they share. OTA-A gives 55.4 dB at 10 Hz.
What limits the input common-mode range of a five-transistor OTA?
Below, the tail leaves saturation when V_CM < V_GS1 + V_Dsat5. Above, the input pair leaves saturation when V_CM > VDD − V_SG3 + V_th1. A PMOS input pair moves the range toward ground; two complementary pairs give rail to rail.
Why does body effect matter in a differential pair?
The pair's sources sit at the tail, above the substrate, so their threshold rises with the input level. That raises V_GS and moves both ICMR edges. Here V_th1 goes from 0.637 V at 0.9 V to 0.702 V at the upper edge.

Try it

Run the netlist. Copy D gives A_d, copy C A_cm, and cmrr10 is their difference in dB. acm_hand is the textbook 1/(2g_m3R_SS) from copy C's operating point. Copies I and S test the two explanations: an ideal tail, and equal drain voltages. kt is how far the tail moves per volt of input, and asym and rterm are the two terms of the common-mode gain, which add up to acm_sum.

Try a longer tail: set L=2 on XMB and XM5 inside .subckt ota. Predict first. Here acm10 gets worse (−11.56 dB): at L = 2 µm M5 needs V_Dsat = 0.180 V and the tail sits at 0.204 V, so it is almost in triode and R_SS falls to 69.3 kΩ. A longer tail helps only with the headroom to use it.

SPICEngspice 42 · simulator service

Edit the netlist, then run it

Expected measurements: ad10 = 4.271332e+01 acm10 = -1.265539e+01 cmrr10 = 5.536871e+01 acm_hand = -2.697164e+01 acmi10 = -1.459980e+01 acms10 = -2.843578e+01

Check yourself

Predict the outputThis is the common-mode half circuit of a resistor-loaded pair as a model: a G source of 1 mS, R_D = 10 kΩ, and 2R_SS = 99 kΩ from source to ground. The gate carries 1 V of AC. Type the line meas prints for the real part of the drain voltage (format: acm = 6.319360e-01).

* the common-mode half circuit as a model: g_m = 1 mS, R_D = 10 k, 2R_SS = 99 k
VIN g 0 dc 0 ac 1
G1 d s g s 1m
RD d 0 10k
RS s 0 99k
.control
ac lin 3 1k 3k
meas ac acm FIND vr(d) AT=1k
.endc
.end

ConceptRead the range plot at V_CM = 0.5 V. What does it show?

M1 has left saturation, because its gate is too lowThe tail still carries about 18 µA, because M5 is a current sourceThe gain is within 2 dB of its mid-range value, but the tail carries under 1 µAThe gain has fallen by more than 20 dB, so the OTA is plainly broken there

ConceptWhy does a follower's error make a poor test of the lower edge of the input range?

The follower's output cannot go below the tail voltage, so it clips firstFollower error is only the offset, and offset never changes with the input levelThe follower measures the upper edge only, because M2 is on the output sideThe loop keeps the error small while the stage starves, since the DC gain holds up

ConceptWhich change raises the upper edge of OTA-A's input range?

A PMOS load with a smaller V_SG, so node x sits higherA longer tail transistor, to raise R_SS and so the tail's output resistanceNarrower input devices, to lower their threshold V_thA larger bias current, to raise every g_m in the circuit

ConceptA bench applies AC 1 to the + input only, holds the − input at AC ground, and reports 42.7 dB as the CMRR. What did it actually measure?

The power-supply rejectionThe differential gainThe CMRR, correctlyThe common-mode gain

Remember

CMRR = A_d/A_cm: drive both inputs together for A_cm and one input for A_d; OTA-A gives 42.71 dB and −12.66 dB, so 55.37 dB.
The hand result 1/(2g_m3R_SS) assumes the two halves match; in a 5T OTA the diode node and the output sit at different voltages, and that asymmetry sets the common-mode gain.
The input range runs from V_GS1 + V_Dsat5 (the tail) to VDD − V_SG3 + V_th1 (the input device): 0.811 V to 1.274 V for OTA-A.
DC gain and follower error hide the lower edge; check saturation margins and the tail current, and remember that speed falls with the current.